SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking a Staff SoC Clock & Power Management Validation Lead for their AI Accelerator Platform team in San Diego. This role involves end-to-end validation of clock, power, reset, and power-management architectures, working closely with cross-functional teams to ensure high-quality silicon across pre- and post-silicon phases. The ideal candidate will have expertise in C, Python, and lab instruments, with a strong background in SoC validation and power management features.

Responsibilities

Own the E2E bare metal framework validation for SoC clock and power architectures.
Develop validation plans, including test strategy and dependencies.
Conduct validation strategy and test plan reviews with stakeholders.
Develop scalable device drivers and system tests using C.
Debug complex issues on pre-Si and post-Si platforms.
Automate the validation process using Python, Perl, and Shell scripting.
Collaborate efficiently with teams in different time zones.

Requirements

Bachelor's degree in engineering (electronics, computer engineering etc.).
5+ years of relevant experience in SoC validation and/or associated areas (SW development, embedded systems etc.).
Prior work experience in clock/power validation.
Proficient in C and Python.
Experienced in using lab instruments (multimeter, oscilloscopes, logic analyzers).
Exposure to debug tools (JTAG etc.) and knowledge of debug methodology for ARM-based SoCs.
Excellent problem-solving, analytical, and debugging skills.

Desired Qualifications

Experience with Cross-Compilers, Linkers, and makefiles.
Understanding of coherency and concurrency in modern SoC architecture.
Knowledge of PMIC/prior experience in validating rail power.
Knowledge of pre-Silicon validation and debug on FPGA-based emulation platforms.
Knowledge of RTL and HDLs (Verilog/System Verilog).
Prior work experience in a cross-functional matrix work environment.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.