Principal D2D SerDes & Analog Layout Design Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is looking for a Principal D2D SerDes & Analog Layout Design Engineer to provide technical leadership for matching-critical analog layout and D2D SerDes physical implementation. This role involves establishing layout strategy, leading complex subsystem execution, influencing architecture, and driving production-ready IP. The position offers broad organizational impact and opportunities to shape long-term layout capabilities for strategic silicon programs.
Responsibilities
- Own the physical implementation strategy and technical execution for complex D2D SerDes and analog/mixed-signal subsystems in advanced process technologies.
- Define top-level D2D analog front-end floorplans and integration strategies.
- Establish matching, isolation, and parasitic-control methodology for critical circuits.
- Lead technical execution across multiple blocks, engineers, and design partners.
- Influence circuit, PHY, package, signal-integrity, physical-design, ESD, CAD, and SoC integration decisions.
- Own resolution of the highest-impact layout risks for transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry.
- Drive physical verification and production-signoff strategy.
- Define and maintain layout quality criteria, review checklists, release requirements, signoff evidence, and technical acceptance criteria.
- Guide delivery of production-ready IP collateral.
- Create and scale reusable analog-layout methodologies, templates, automation flows, and productivity solutions using SKILL, TCL, Python, Cadence APR, or similar technologies.
- Provide technical direction and mentorship to senior engineers and partner teams.
- Govern technical execution with contractors, vendors, and geographically distributed design partners.
- Communicate technical strategy, status, risks, options, and recommendations to engineering and program leadership.
- Identify longer-term technology, methodology, staffing, and enablement needs for future D2D and analog IP generations.
Requirements
- Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
- Ability to meet Microsoft, customer and/or government security screening requirements.
- Microsoft Cloud Background Check.
Desired Qualifications
- 8+ years of analog or mixed-signal layout experience, including matching-critical transistor-level layout and complex subsystem integration in advanced process technologies.
- Experience leading analog, mixed-signal, SerDes, or D2D IP physical implementation through floorplanning, verification, signoff, tapeout, and integration.
- Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools.
- Experience with DRC, LVS, ERC, antenna, extraction-aware layout, EMIR or reliability considerations, and advanced-node physical signoff.
- Experience providing technical leadership across multiple layout contributors and influencing circuit design, CAD, package, signal-integrity, physical-design, or SoC integration teams.
- Deep experience with high-speed SerDes, D2D interfaces, or comparable high-performance analog/mixed-signal IP.
- Demonstrated expertise in analog matching, symmetry, layout-dependent effects, device orientation, process gradients, coupling, isolation, shielding, return paths, and parasitic optimization.
- Experience with D2D standards or implementations such as UCIe, BoW, or proprietary die-to-die links.
- Experience defining physical implementation strategy for advanced packaging and chiplet integration.
- Experience influencing circuit, interface, floorplan, or package decisions based on implementation feasibility, extraction, EMIR, reliability, and system-level tradeoffs.
- Experience leading top-level assembly and verification of analog subsystems developed by multiple engineers, organizations, or external partners.
- Experience with EMIR and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools.
- Experience with Cadence automated place-and-route (APR) flows.
- Strong automation and methodology-development skills using Python, SKILL, TCL, Perl, or similar languages.
- Experience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm, 3nm, or beyond.
- Demonstrated success mentoring senior engineers, establishing technical standards, resolving complex cross-organizational issues, and influencing engineering leadership.
- Experience governing technical delivery across geographically distributed teams, contractors, vendors, or design-service partners over multiple milestones or programs.
Benefits
- Typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year.
- Different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, where the base pay range is USD $188,000 - $304,200 per year.
- Certain roles may be eligible for benefits and other compensation.
- Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay
Skills
SerDesAnalog LayoutMixed-SignalCadence VirtuosoCalibreDRCLVSERCPythonSKILLTCL
#Hardware Engineering#Silicon Engineering#D2D SerDes#Analog Layout#Mixed-Signal IP#Advanced Process Technologies#Physical Implementation#Tapeout#SoC Integration#Physical Verification#FinFET#Gate-All-Around
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Company
MicrosoftJob Posted
3 days ago
Employment Type
Full Time
Work mode
Hybrid
Salary
US$142,800–274,800 · Negotiable
Experience Level
Senior
Locations
United States
Qualification
Doctoral, Master, Bachelor
Applicants
Be an early applicant
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