SoC Physical Design Engineer (Senior to Principal)

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm Vietnam is looking for a Senior to Principal Physical Design Engineer to lead technical aspects of physical implementation on advanced FinFET nodes. This role involves defining backend design methodology, integrating AI into the PD flow, and mentoring engineers.

Responsibilities

Leverages advanced ASIC knowledge and experience to define, model, design (digital, analog and/or mix signal), optimize, verify, validate and implement IP (block/SoC) development for a variety of high performance, high quality, low power products.
Participates in or leads the design implementation of advanced design rules and processes for electronic hardware, equipment, and/or integrated circuitry.
Conducts highly complex simulations and analyses of designs as well as implements designs with the best power, performance, and area.
Evaluates all aspects of complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
Utilizes tools/applications (e.g., RTL to GDS Flow) to execute and enable advanced architecture and design of multiple complex blocks/SoC or IC Packages.
Writes and reviews detailed technical documentation for complex EDA/IP/ASIC projects.

Requirements

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.
Master's degree in Science, Engineering, or related field and 3+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.
Master's degree in VLSI, Electrical/Electronic Engineering, Physic Engineering, Computer Engineering, or Computer Science with 3+ years of experience.
Deep expertise in full chip and block level floor-planning, design implementation through place and route, ECO, STA, LEC / Timing / Power closure, and Physical Verification.
Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF).
Advanced Shell, Python and Tcl scripting: ability to architect large-scale SOC back-end automation frameworks and flow infrastructure.
Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges: autonomous agents, AI-driven optimization, LLM-assisted debugging.
Strong communication skills: ability to present methodology decisions, risk assessments, and tape out readiness to senior management.

Desired Qualifications

Years of experience: 4-88+
Previous roles: Senior Design Engineer, Senior Engineer, Principal Engineer, Lead Engineer, Engineer

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.

Skills

ASIC physical designECOSTAphysical verificationpower analysisVLSIElectrical EngineeringPhysic EngineeringComputer EngineeringComputer Sciencefloor-planningplace and routeTiming closurePower closurepower optimizationDVFSmulti-Vtpower domainsUPFCPFShell scriptingPythonTcl scriptingautomationAIRTL to GDS Flow

#SoC#Physical Design#ASIC#Hardware Engineering#FinFET