ASIC Digital Design, Sr Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys is seeking a Senior ASIC Digital Design Engineer to design and develop bare metal firmware for SerDes IP. The role involves close collaboration with mixed-signal teams, silicon bring-up, and mentoring junior engineers, with a focus on structured development processes and AI tool utilization.

Responsibilities

Design, develop, and validate bare metal firmware for NRZ and PAM-based SerDes IP targeting high-speed data recovery and serialization circuits.
Work directly with mixed-signal design and verification teams to integrate firmware with analog and digital subsystems from spec through silicon bring-up.
Execute silicon bring-up on prototype test chips, diagnosing and resolving functional and performance issues between RTL behavior and actual hardware.
Mentor junior firmware and digital design engineers on structured development flows, RTL debugging, and bring-up best practices.
Drive firmware development using structured processes including documentation, version control, and verification handoffs.
Collaborate with customer support and design groups to resolve integration issues and support SerDes IP deployment into customer SoCs.
Leverage AI tools like Cursor to accelerate development, debugging, and code quality without sacrificing rigor.

Requirements

Bachelor's or Master's in Electrical Engineering or equivalent practical experience.
5+ years of hands-on experience in bare metal firmware development and silicon bring-up.
Strong digital design skills with deep understanding of RTL, synthesis, and timing closure.
Demonstrated ability to mentor engineers and provide technical leadership on complex projects.
Experience executing firmware projects from specification through silicon validation using structured development and verification processes.
Ability to work across design groups and customer support teams with clear, effective communication.
Knowledge of SerDes, Ethernet, or PCIe standards is a strong plus.
Proficiency with AI tools like Cursor for accelerating development workflows is a plus.

Desired Qualifications

You can explain a register map conflict to a mixed-signal designer in two sentences without losing the technical nuance.
When a prototype does not match simulation, you methodically isolate the issue rather than guessing or escalating prematurely.
You balance design quality with deadlines, knowing when to push back and when to ship with documented trade-offs.
You treat documentation as part of the deliverable, not an afterthought.
You are comfortable diving into unfamiliar territory, whether that is a new SerDes standard or a silicon bug that does not match any known pattern.
You stay current with tooling and methods, including AI-assisted development, and apply them where they genuinely improve outcomes.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement plans.
Competitive salaries.

Skills

RTLfirmwareSerDesverificationmixed-signalsynthesystiming closurePythonC++Cursor

#ASIC#Digital Design#Sr Engineer

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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