Senior System Design Architect

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Qualcomm is seeking a Senior System Design Architect to join their Cloud System Hardware Engineering team in Taipei. This role focuses on developing advanced rack-level AI inference solutions for next-generation data centers, requiring design and development of motherboards, add-in cards, and modules for new AI SoCs/SIPs.

Ansvarsområden

Design and develop motherboards/add in cards/modules for Qualcomm new AI System On Chip (SoC)/System In Package (SIP).
Work with cross-functional teams (thermal, SI, PTE, regulatory, validation, manufacturing, etc.) and ODMs for project execution from concept to production.
Support rack level design and integration of cards, servers and networking switches.
Address technical focus areas including data center system architecture, rack/chassis/motherboard standards, modular systems, platform compliance, and accelerator integration.

Krav

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Demonstrated ability to influence across teams and organizations.
Strong communication, collaboration, and stakeholder engagement skills.

Önskade kvalifikationer

Experience in system design, validation, or related engineering roles.
Understanding of data center system architecture.
Familiarity with rack, chassis, and motherboard standards (mechanical and infrastructure design).
Knowledge of modular systems (e.g., PCIe add-in cards, MHS, and similar form factors).
Experience with platform compliance, modeling, and validation.
Expertise in accelerator integration within AI rack platforms.
Knowledge of SoC/IP integration, memory technologies, and high-speed I/O interconnects.
Understanding of mechanical implications for high TDP CPUs/GPUs/AI accelerators and memory (HBM, DIMM density).
Experience with connector and retention design.
Understanding of signal integrity impacts of: Board warpage, Connector placement, Cable routing / risers.
Knowledge of mechanical implications for air and liquid (DLC) power, chips and memory thermal needs.
Familiarity with quick disconnect (MQD), blind mate electrical, liquid and modern interface design.