Senior Lead Physical Design Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

I korthet

Qualcomm is seeking a Senior Lead Physical Design Engineer in Noida, India, to own PNR implementation for SoC's on latest nodes. The role requires extensive experience in Floorplanning, PNR, STA, and signoff domains, with strong Unix/Linux and scripting skills.

Ansvarsområden

Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route,etc) on latest nodes.
PNR implementation for Qualcomm SoC's
Plan, design, optimize, verify, and test electronic systems, circuits, and packaging.

Krav

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
5+ years Hardware Engineering experience or related work experience.
5+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm)
Good hands-on experience on Floorplanning, PNR and STA flows
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc
Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)

Önskade kvalifikationer

Quick learner with good analytical and problem-solving skills

Förmåner

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Färdigheter

Hardware EngineeringFloorplanningPNRSTAPlacementClock Tree Synthesis (CTS)LECCLPPDNUnix/LinuxPerlTCLPower analysisFVlow power verificationPVASIC DesignASICAutomationCompilers

#SoC#PNR implementation#Physical Design#Floorplanning#Placement#Clock Tree Synthesis#STA#Signoff#LEC#CLP#PDN#Unix/Linux#Perl#TCL#Hardware Engineering#ASIC Design