Senior Design Lead

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Join HCLTech as a Senior Design Lead in Bangalore, India. This role requires 5-7 years of experience in ASIC/SoC verification, including testbench architecture, UVM-based development, and gate-level simulations. You will be responsible for developing and maintaining testbenches, executing test cases, and performing regression analysis.

Ansvarsområden

Define Full Chip TB Architecture.
Write ASIC/SoC testplans.
Develop UVM based testbench.
Build and maintain reusable block-level and sub-system testbenches using SystemVerilog and UVM.
Write, execute, and debug constrained-random and directed test cases.
Develop TB components for SOC with C and SV.
Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics.
Debug complex simulation failures using waveform viewer tools.
Perform Gate level simulation & netlist debugging.
Perform regression failure analysis.
Work on functional and code coverage closure.
Participate in verification closure.
Use scripting languages like Python, Tcl, or Perl for automation.

Krav

5 to 7 years of experience is mandatory.
Good understanding of ASIC/SoC life cycle.
Participated in multiple ASIC/SoC verification till tapeout stage.
Experience writing ASIC/SoC testplans.
Experience in ASIC/SoC Testbench definition.
Expertise & hands-on experience in OVM/UVM methodologies using SV.
Experience in developing TB components, including functional coverage implementation and assertion coding.
Experience Set up functional coverage, write system assertions (SVA), and analyze code coverage metrics to identify untested gaps in the design logic.
Experience in SOC C based tests coding & debugging.
Experience in Gate level simulation & netlist debugging.
Experience in regression failure analysis.
Proficiency in Verilog, SystemVerilog, and core concepts of UVM.
Strong foundational knowledge in digital logic design, finite state machines (FSM), FIFO architectures, and clocking concepts.
Familiarity with industry-standard simulation and debugging tools (e.g., Synopsys VCS, Siemens QuestaSim, Cadence Xcelium/Verdi).
Deep, authoritative knowledge of high-speed protocols (e.g., SPI, I2C, PCIe, NVMe, Ethernet, USB) or complex bus architectures (e.g., AMBA AXI/CHI/ACE).

Önskade kvalifikationer

Bachelor's or Master's degree in Electronics & Communication Engineering (ECE), Electrical Engineering (EE), VLSI Design, or a closely related field.
Basic comfort working in a Linux environment and using scripting languages like Python, Tcl, or Perl for automation.

Förmåner

Supercharge your potential.
Find your career.
Find your spark.
A place that knows that helping its customers stay on top starts by putting its people first.
Global technology company, home to more than 223,000 people across 60 countries.
Delivering industry-leading capabilities centered around digital, engineering, cloud and AI.
Consolidated revenues as of 12 months ending June 2026 totaled $14.8 billion.

Färdigheter

SystemVerilogUVMVerilogOVMPerlShell scriptingPythonTclSPII2CPCIeNVMeEthernetUSBAMBA AXIAMBA CHIAMBA ACESynopsys VCSSiemens QuestaSimCadence XceliumCadence Verdi

#ASIC#SoC#Verification#UVM#SystemVerilog#Testbench#Scripting#Digital Logic#Protocols#EDA Tools

Om HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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