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Server CPU Clock Physical Design Engineer, Staff level - Cambridge, UK

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

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Qualcomm seeks an experienced CPU Clock Physical Design Engineer for its Nuvia Data Center CPU team in Cambridge, UK. This role focuses on defining, implementing, and optimizing clock generation and distribution solutions for high-performance, power-efficient custom CPU technology for server-class platforms. The position offers technical leadership and ownership for Staff Engineer level candidates.

Ansvarsområden

  • Define and drive the overall clock generation and clock distribution methodology for next-generation data center CPU designs.
  • Work with microarchitecture, RTL, CAD, circuit, block-level physical design, and top-level physical design teams to understand, implement, and validate CPU clocking requirements.
  • Architect, implement, and optimize low-skew, low-power clock networks using approaches such as clock H-trees, clock mesh, clock spines clocking methodologies.
  • Partner with CAD and physical design teams to develop and deploy clocking techniques that optimize skew, latency, clock power, timing margin, routability, and design convergence.
  • Use SPICE simulation and circuit-level analysis to validate clock circuits, clock paths, and electrical behaviour across process, voltage, and temperature conditions.
  • Analyse and debug clock-related timing, power, noise, variation, and physical implementation issues across multiple modes, corners, and operating conditions.
  • Provide feedback and guidance to block-level and top-level physical design engineers on required clocking fixes, optimization opportunities, and signoff risks.
  • Collaborate with PLL, timing, power, CAD, and implementation teams to align clock source assumptions, jitter budgets, clock uncertainty, and signoff methodology.
  • Develop, document, and improve clock construction, analysis, and validation flows for future CPU generations.
  • For Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of critical clocking challenges.

Krav

  • Strong experience in CPU clocking, physical design, timing, and circuit-aware implementation.
  • Strong experience in the construction and analysis of low-skew and low-power clock generation and distribution networks.
  • Hands-on experience with clock distribution structures and methodologies such as Clock H-tree, Clock Mesh, Clock Spines
  • Strong understanding of CTS, clock balancing, insertion delay, skew optimization, useful skew, clock power reduction, and clock latency trade-offs.
  • Good understanding of device physics, RC delay, signal integrity, variation, and electrical effects that influence clock quality and timing robustness.
  • Proficiency in SPICE simulation and analysis for circuit design, clock-path validation, and electrical verification.
  • Strong understanding of static timing analysis and the interaction between clock architecture, timing closure, jitter, uncertainty, OCV/AOCV/POCV, setup/hold closure, and signoff quality.
  • Ability to debug complex clocking issues across implementation, timing, power, noise, variation, and circuit domains.
  • Experience working with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.
  • Strong communication skills and the ability to work effectively with global, cross-functional engineering teams.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
  • OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.
  • OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.

Önskade kvalifikationer

  • Experience defining or deploying clock methodology across multiple designs, projects, or technology generations.
  • Strong background in chip-level or top-level physical design, block integration, standard-cell optimization, and clock construction.
  • Experience working in advanced semiconductor process nodes, especially 7nm and below.
  • Proficiency with PLL specifications, clock source modelling, skew estimation, jitter budgeting, and jitter measurements. Experience with high-frequency CPU or high-performance compute clocking.
  • Experience with power-aware clocking, clock gating, resonant or mesh-based clocking strategies, and clock power optimization.
  • Familiarity with multi-corner multi-mode timing closure and variation-aware implementation methodologies.
  • Experience developing automation or analysis flows using TCL, Python, Perl, or similar scripting languages.
  • For Staff-level candidates, demonstrated ability to lead technical initiatives, influence cross-functional teams, define methodology, and mentor other engineers.

Förmåner

  • Competitive compensation package, including base salary, performance-related bonus, and equity opportunities.
  • Employee Stock Purchase Plan and equity programs supporting employee share ownership and long-term participation in Qualcomm’s success.
  • Pension and retirement support, including a matching pension scheme.
  • Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.
  • Maternity, paternity, family, and extended leave support to help employees balance professional and personal commitments.
  • Education assistance and tuition support to enable continued learning and professional development.
  • Relocation and immigration support where applicable, particularly for strong candidates moving to join the Cambridge team.
  • Employee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.
  • Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion, collaboration, and community engagement.
  • Subsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.
  • A flexible, collaborative, and technically challenging work environment, with the opportunity to work alongside highly skilled engineers on advanced CPU technology.

Färdigheter

CPU clockingphysical designtimingcircuit-aware implementationClock H-treeClock meshClock spinesSPICE simulationstatic timing analysisTCLPythonPerl
#CPU#Clocking#Physical Design#STA#EDA#Server
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Företag

Qualcomm

Publicerade jobb

för 1 dag sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Cambridge, United Kingdom

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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