IP Design - Lead engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Qualcomm is seeking an experienced Lead IP Design Engineer in Chennai, India. This role requires 8+ years of experience in IP/SoC design, micro-architecture, and understanding of interconnect protocols and multi-core ARM architectures. The engineer will manage design tasks, drive project milestones, and possess strong communication and leadership skills.

Ansvarsområden

Manage SoC dependencies, planning and tracking of all front-end design related tasks.
Driving project milestones across the design, verification and physical implementations.
Understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification.

Krav

8+ years of solid experience in IP/SoC design and micro-architecture
Understanding of interconnect protocols like CHI/AHB/AXI/ACE/ACE-Lite/NoC concepts
Good knowledge of Digital Design and RTL development
Hands-on experience with SoC Design, Verilog RTL coding
Understanding of multi-core ARMv8/v9 CPU architecture, coherency protocols and virtualization.
Working knowledge of Synthesis, DC/DCG synthesis with Synopsys design complier, DFT, verification, formal verification, silicon debug
Working knowledge of Lint, CDC, PLDRC, CLP etc
Should possess effective communication and leadership skills
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Färdigheter

VerilogARMv8AXIARMv9AHBCHIACEACE-Lite

#IP Design#SoC design#micro-architecture#interconnect protocols#RTL development#ARMv8#ARMv9#CPU architecture#coherency protocols#virtualization#Synthesis#timing closure#verification#silicon debug#lint#CDC#PLDRC#CLP#design convergence#lead engineer