DDR Design Verification Staff Engineer

We are seeking a skilled Design Verification (DV) engineer for LPDDR/DDR based IPs and Subsystems. The role involves creating DV infrastructure, integrating VIPs, executing test plans, debugging failures, and ensuring high-quality verification. This position requires a strong understanding of digital design concepts, DV methodologies, and DDR/LPDDR families, along with proficiency in System Verilog and UVM.