Silicon Micro Architecture and IP Design Lead, Google Cloud

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Lead the development of complex IPs and subsystems, owning micro-architecture and implementation. This role involves collaborating with architecture, firmware, and software teams to define specifications and drive design methodology, debug, and code review. Focus on power, performance, and area improvements for AI/ML hardware acceleration and TPU technology.

Responsibilities

Drive development of complex IPs and subsystems along with a team of engineers.
Own micro-architecture and implementation of IPs and subsystems.
Work with architecture, firmware and software teams to drive feature closure and develop micro-architecture specifications.
Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams.
Identify and drive power, performance and area improvements for the domains owned.

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
10 years of experience in ASIC development with Verilog/SystemVerilog, and Vhsic Hardware Description Language (VHDL).
Experience in micro-architecture and design of IPs and Subsystems.
Experience in ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT).

Desired Qualifications

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience with scripting languages (e.g., Python or Perl).
Experience in SoC designs and integration flows.
Knowledge of business architectures, fabrics/NoC, processor design, accelerators, or memory hierarchies.
Knowledge of high-performance and low-power design techniques.

Benefits

Equity is granted exclusively and discretionarily by Alphabet Inc.
Google is proud to be an equal opportunity and affirmative action employer.
See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire.
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form.
English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Skills

VerilogSystemVerilogVHDLPythonPerl

#silicon#micro architecture#IP design#Google Cloud#AI/ML hardware acceleration#TPU#ASIC development#Verilog#SystemVerilog#VHDL#design verification#synthesis#timing analysis#power analysis#DFT#SoC designs#scripting languages#Python#Perl#computer architecture#high-performance design#low-power design

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