Design Engineer (Low Power)
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
Qualcomm Atheros is seeking a Design Engineer specializing in Low Power for their Santa Clara, CA location. This role involves developing technical specifications, low power micro-architecture, and design for WiFi and SOC technologies. Responsibilities include RTL implementation, verification, synthesis, timing closure, emulation, silicon bring-up, debug, and power measurements.
Responsibilities
- Develop technical specifications from Architectural and systems requirements.
- Deliver detailed low power micro-architecture and design.
- Work closely with the verification team to develop verification plans.
- Actively participate in the debug phase.
- Own design through the full ASIC development process: specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring up.
- Responsible for silicon power measurements, Si debug, and power correlation.
- Responsible for full chip debug design using ARM IPs.
Requirements
- 7+ years of working experience in ASIC Design
- 2+ years of Experience in low power micro-architecture, Design, Power Intent/Implementation, power optimization and power estimation
- Experience in silicon bring up and debug is a must
- Required experience on SoC micro architecture, multi-domain clocking, AMBA bus protocols such as AHB and APB. AXI is preferred
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Desired Qualifications
- Experience in ARM IP based full chip debug is preferred.
- Experience in PCIE/USB peripherals is preferred.
- Experience in CPU sub system-based design is preferred.
- Experience in low power design from project start to volume chip production for at least one product cycle is preferred.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Skills
ASIC DesignLow Power DesignRTLMicro-architecturePower IntentPower EstimatesPower ReductionARM IPSoCClockingAMBAAHBAPBAXIPCIEUSBCPU
#ASIC Design#Low Power#Micro-architecture#Power Intent#Power Estimates#Power Reduction#ARM IP#SoC#Clocking#AMBA#AHB#APB#AXI#PCIE#USB#CPU
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
4 days ago
Employment Type
Full Time
Work mode
On Site
Salary
US$190,200–285,400 / year
Experience Level
Senior
Locations
Santa Clara, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
Similar Jobs
Ericsson
Lund, SwedenMaster Thesis: Early Prediction and Optimization of power, Perfomance and Area
Internship Be an early applicant Posted 4 days ago
IKEA
Sligo, IrelandSales Specialist - IKEA Sligo
€33.8k/yr Full Time Be an early applicant Posted 4 days ago
Saab
Fareham, United KingdomField Support Technician
Full Time Be an early applicant Posted 4 days ago
ABB
Vaesteras, SwedenThesis Work on Post-Fault Recovery Stability of AI Data Center in Weak Grids
Internship Be an early applicant Posted 4 days ago
Microsoft
Romania +1 moreSenior Technical Support Engineer
€43.3–74.3k/yr Full Time Be an early applicant Posted 4 days ago
Electrolux Group
EuropeHR Data Analyst, Operations EMEA & APAC
€45.2k/yr Full Time Be an early applicant Posted 4 days ago