Design Engineer (Low Power)
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I korthet
Qualcomm Atheros is seeking a Design Engineer specializing in Low Power for their Santa Clara, CA location. This role involves developing technical specifications, low power micro-architecture, and design for WiFi and SOC technologies. Responsibilities include RTL implementation, verification, synthesis, timing closure, emulation, silicon bring-up, debug, and power measurements.
Ansvarsområden
- Develop technical specifications from Architectural and systems requirements.
- Deliver detailed low power micro-architecture and design.
- Work closely with the verification team to develop verification plans.
- Actively participate in the debug phase.
- Own design through the full ASIC development process: specification, RTL implementation, verification, synthesis, timing closure, emulation, and post-silicon bring up.
- Responsible for silicon power measurements, Si debug, and power correlation.
- Responsible for full chip debug design using ARM IPs.
Krav
- 7+ years of working experience in ASIC Design
- 2+ years of Experience in low power micro-architecture, Design, Power Intent/Implementation, power optimization and power estimation
- Experience in silicon bring up and debug is a must
- Required experience on SoC micro architecture, multi-domain clocking, AMBA bus protocols such as AHB and APB. AXI is preferred
- Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
- OR Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
- OR PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Önskade kvalifikationer
- Experience in ARM IP based full chip debug is preferred.
- Experience in PCIE/USB peripherals is preferred.
- Experience in CPU sub system-based design is preferred.
- Experience in low power design from project start to volume chip production for at least one product cycle is preferred.
Förmåner
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Färdigheter
ASIC DesignLow Power DesignRTLMicro-architecturePower IntentPower EstimatesPower ReductionARM IPSoCClockingAMBAAHBAPBAXIPCIEUSBCPU
#ASIC Design#Low Power#Micro-architecture#Power Intent#Power Estimates#Power Reduction#ARM IP#SoC#Clocking#AMBA#AHB#APB#AXI#PCIE#USB#CPU
Om Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Företag
QualcommPublicerade jobb
för 3 dagar sedan
Anställningstyp
Heltid
Arbetsform
På plats
Lön
190 200–285 400 US$ / år
Erfarenhetsnivå
Senior
Platser
Santa Clara, United States of America
Kvalifikation
Kandidatexamen, Masterexamen, Doktorand
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