Senior Technical Architect

Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering

In short

Senior Technical Architect position in Bangalore, India, requiring B.Tech/M.Tech in Electrical or Electronics Engineering and 15-20 years of experience. Responsibilities include end-to-end physical design flow, achieving timing closure, resolving violations, and handling low-power design techniques.

Responsibilities

Perform end-to-end physical design flow: Floorplanning, Power planning (PG grid, IR), Placement & optimization, CTS (Clock Tree Synthesis), Routing, Post-route optimization
Achieve timing closure across all modes and corners
Resolve DRC, LVS, ERC and signoff violations
Handle low-power design techniques: Multi-Vt, Multi-voltage (UPF), Power gating, clock gating
Perform physical verification and signoff: STA (Primetime), SI / Crosstalk, IR drop & EM analysis
Work on advanced nodes (7nm, 5nm, 3nm or below)
Collaborate with RTL & Micro-architecture teams, DFT & Test engineers, Foundry and CAD teams
Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)
Own full-chip STA signoff for all PVT corners and modes (functional, scan, low-power, etc.)
Drive timing closure at chip level, including setup/hold, noise, OCV/AOCV/POCV

Requirements

B.Tech / M.Tech in Electrical or Electronics Engineering.
Experience: 15 to 20 years

Desired Qualifications

Experience with advanced nodes (7nm, 5nm, 3nm or below)
Experience with low-power design techniques: Multi-Vt, Multi-voltage (UPF), Power gating, clock gating
Experience with physical verification and signoff: STA (Primetime), SI / Crosstalk, IR drop & EM analysis

Benefits

Supercharge your potential
Find your career
Find your spark
A place that knows that helping its customers stay on top starts by putting its people first.

Skills

Power planningClock Tree SynthesisRoutingSTAPrimetimeUPFPower gatingClock gatingDRCLVSERCSIIR dropEM analysisDFTAutomationScripts

#Technical Architect#Physical Design#Floorplanning#Power Planning#Placement#CTS#Routing#Timing Closure#DRC#LVS#ERC#Low-power design#STA#Primetime#SI#IR drop#EM analysis#Advanced nodes#RTL#Micro-architecture#DFT#Foundry#CAD#Chip-level STA#Setup/Hold#Noise#OCV#AOCV#POCV

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