Physical Design Engineer- Staff to Sr. Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a highly experienced Clock Physical Design Engineer to join their NSP Physical Design Team. This role focuses on developing, optimizing, and signing off advanced clocking solutions for next-generation designs, requiring expertise in clock H-trees, clock mesh, and clock spine methodologies. The engineer will collaborate with various teams to optimize clock performance, power, and robustness across advanced technology nodes.

Responsibilities

Own and drive clock physical design methodology, implementation, optimization, and signoff for complex NSP designs.
Architect, implement, and optimize advanced clock distribution structures, including Clock H-trees, Clock mesh architectures, Clock spine methodologies, Hierarchical clock distribution, and Clock gating techniques.
Perform detailed SPICE simulation and transistor-level analysis of critical clock structures.
Analyze and debug clock-related issues such as timing, power, signal integrity, noise, variation, jitter, duty-cycle distortion, slew, and routing issues.
Drive clock convergence and signoff across multiple modes, process corners, voltage conditions, temperatures, and operating frequencies.
Analyze clock distribution tradeoffs across performance, power, area, skew, insertion delay, variation, and robustness.
Provide technical feedback and guidance to block-level and top-level Physical Design engineers.
Collaborate closely with PLL, STA/timing, power, CAD, RTL, architecture, and implementation teams.
Perform detailed clock timing analysis using Synopsys PrimeTime and correlate results.
Develop and tune customized clock implementation recipes and methodologies.
Support clock-related ECO development and implementation during timing closure and tapeout convergence.
Evaluate clock networks for IR-drop, EM, crosstalk, signal integrity, and reliability risks.
Drive clock tapeout readiness and ensure all clock structures meet signoff criteria.
Develop and enhance clock analysis, debug, characterization, and implementation automation using TCL, Python, Perl, and Linux shell scripting.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
10+ years of industry experience in ASIC/SoC Physical Design.
Significant hands-on experience in high-performance clock implementation and timing closure.
Proven experience taking complex ASIC/SoC designs through physical design convergence and successful tapeout.
Deep hands-on expertise with advanced clock distribution methodologies, including Clock H-trees, Clock mesh, Clock spines, Hierarchical clock distribution, and Clock gating and low-power clock implementation.
Strong understanding of clock skew, insertion delay, jitter, clock uncertainty, slew, duty-cycle distortion, PVT, on-chip variation, clock power optimization, clock signal integrity, clock-related IR/EM concerns, and multi-mode/multi-corner timing analysis.
Hands-on experience with SPICE simulation and the ability to analyze clock circuits and distribution structures at the transistor and waveform level.
Strong experience with Synopsys Fusion Compiler / ICC2 and/or Cadence Innovus, Synopsys PrimeTime, RC extraction and signal-integrity analysis tools, and physical verification and DRC/LVS signoff flows.
Strong understanding of advanced-node timing, parasitics, variation, power integrity, and reliability effects on clock distribution.
Proficiency in TCL, Python, Perl, and Linux/Unix environments.

Desired Qualifications

Experience developing and deploying custom clock methodologies for high-frequency designs rather than relying exclusively on conventional CTS approaches.
Experience with advanced technology nodes and clock-design challenges associated with increased process variation, interconnect resistance, power density, and reduced voltage margins.
Strong understanding of PLL behavior, jitter, clock-source modeling, and clock uncertainty budgeting.
Experience correlating SPICE, STA, extraction, and physical implementation results to identify root causes of clock performance or signoff issues. Familiarity with Infinisim or PrimeClock a plus.
Knowledge of dynamic power, IR-drop, electromigration, signal integrity, crosstalk, and reliability analysis as they relate specifically to high-performance clock networks.
Experience working across hierarchical SoC implementation, including interaction between clock source, top-level clock distribution, and block-level clock networks.
Ability to influence implementation methodology and provide clear technical guidance to block owners, top-level PD engineers, timing teams, and CAD teams.
Strong analytical and debugging skills with the ability to drive complex clocking problems from initial characterization through root cause and final signoff.

Benefits

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support your success at work, at home, and at play.
Information about US benefits available at a provided link.
The provided pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location.
Pay range: $174,400.00 - $261,600.00.

Skills

ASICSPICE simulationSynopsys PrimeTimeTCLPythonPerlLinuxSynopsys Fusion CompilerCadence Innovus

#ASIC#Clock#Physical Design#STA#Timing#Power#PLL#CAD

About Qualcomm

Enabling a world where everyone and everything can be intelligently connected.

Enabling a world where everyone and everything can be intelligently connected.\n\n

See all open jobs at Qualcomm Read more about Qualcomm Website

Company

Qualcomm

Job Posted

6 days ago

Employment Type

Full Time

Work mode

On Site

Salary

US$174,400–261,600 / year

Experience Level

Senior

Locations

Austin, United States of America

Qualification

Bachelor, Master, Doctoral, Undergraduate

Applicants

Be an early applicant

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