Director , Engineering (GPU Physical Design)

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm is looking for a Director of Engineering specializing in GPU Physical Design in Bangalore, India. This role involves leading teams in the development of high-performance ASIC products, focusing on physical implementation activities and PPA critical core convergence.

Responsibilities

Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products.
Collaborate with cross-functional groups to determine product execution path.
Lead physical implementation activities for high performance GPU Cores, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization.
Make PPA trade-off decisions for PPA critical Cores.
Achieve timing convergence for high frequency data-path intensive Cores and apply advanced STA concepts.
Perform Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes.
Work in close collaboration with design, DFT and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc.
Handle technical deliverables with a small team of engineers.
Work towards project milestones and deadlines.

Requirements

Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
Bachelor's/Master’s degree in Electrical/Electronic Engineering from a reputed institution.
20+ years of experience in Physical Design/Implementation.
10 years of experience in leading a team working on high performance cores.
Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts.
Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes.
Good understanding of clocking architecture.
Well versed with Tcl/Perl Scripting.
Strong problem-solving skills.
Good communication skills.

Desired Qualifications

Experience of working as part of a larger team.
Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc.

Skills

ASIC designASIC verificationASIC validationASIC integrationFloor-planningPlace and RouteCTSFormal verificationDRCLVSPDNTiming ClosurePower optimizationSTASynopsys ICC2Cadence InnovusPTSITempusTclPerlGPU

#ASIC#GPU#Physical Design#Engineering