SOC Limits Management Architect
Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering
In short
As a SoC Limits Management Architect on the HW power team, you will define how our next-generation systems balance high performance against physical, electrical and thermal constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic Limits Management architecture solution. This role ensures SoCs deliver maximum performance under peak current, power and thermal constraints while maintaining long-term reliability and stability.
Responsibilities
- Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
- Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
- Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
- Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
- Drive organizational consensus on feature return on investment (ROI) and oversee Post-Silicon Validation to ensure physical silicon behavior aligns with architectural intent.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
- 15 years of industry experience in Power Management or Low-Power Design/Methodology.
- Experience navigating the full product delivery cycle, from initial architecture definition through to post-silicon productization.
- Experience with low-power architectures and advanced power optimization techniques.
Desired Qualifications
- MS or PhD in Electronics or Computer Engineering, or equivalent, with a focus on computer architecture and power/performance analysis.
- Experience in peak power management, power budgeting, in-rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management and AI.
- Exceptional leadership and influencing skills, with an ability to influence cross-functional roadmaps and drive ROI-based technical decisions.
Benefits
- Competitive annual discretionary bonus program
- Opportunity for annual RSU grants
- Highly competitive benefits package designed to support your success at work, at home, and at play.
Skills
ASIC designASIC verificationASIC validationASIC integrationPower ManagementLow-Power DesignLow-Power Methodologypower budgetingin-rush currentPDN droop detectionmitigationadaptive clock distributionaging and process monitorspower aware floorplanningbattery technologyconcurrency managementthermal managementAI
#ASIC Engineering#SoC Limits Management
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
1 day ago
Employment Type
Full Time
Work mode
On Site
Salary
US$174,400–261,600 / year
Experience Level
Executive
Locations
San Diego, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
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