CPU STA Engineer, Sr Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking a Sr. Engineer for their CPU STA role in Hyderabad, India. This position involves planning, designing, optimizing, verifying, and testing electronic systems, with a strong emphasis on Static Timing Analysis (STA) for high-speed CPU implementations. A Bachelor's degree in a related field and at least 2 years of relevant experience are required.

Responsibilities

Plan, design, optimize, verify, and test electronic systems.
Bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems.
Develop solutions and meet performance requirements by collaborating with cross-functional teams.
Complete ASIC flow with low power, performance and area optimization techniques.
Experience with STA using Primetime and/or Tempus is required.
Proficient in constraint generation and validation.
Experience of multiple power domain implementation with complex UPF/CPF definition required.
Formal verification experience (Formality/Conformal).
Experience with CPU micro-architecture and their critical path.
Low power implementation techniques experience.
High speed CPU implementation.
Clock Tree Implementation Techniques for High Speed Design Implementation are required.
Exposure to Constraint management tool and Verilog coding experience.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
Extensive experience in Place & Route with FC or Innovus is an absolute must.
Experience with STA using Primetime and/or Tempus is required.
Proficient in constraint generation and validation.
Experience of multiple power domain implementation with complex UPF/CPF definition required.
Formal verification experience (Formality/Conformal).
Perl/Tcl, Python, C++ skills are needed.
Strong problem solving and ASIC development/debugging skills.
Experience with CPU micro-architecture and their critical path.
Low power implementation techniques experience.
High speed CPU implementation.
Clock Tree Implementation Techniques for High Speed Design Implementation are required.
Exposure to Constraint management tool and Verilog coding experience.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

Place & RouteFCInnovuslow powerperformance optimizationarea optimizationSTAPrimetimeTempusconstraint generationconstraint validationUPFCPFFormal verificationFormalityConformalPerlTclPythonC++ASIC developmentCPU micro-architecturecritical pathClock Tree ImplementationConstraint management toolVerilog

#CPU#STA#Engineer#Hardware Engineering#ASIC