Principal Physical Design Engineer

Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering

In short

Microsoft seeks a Principal Physical Design Engineer to lead end-to-end physical design flows for state-of-the-art computer chips, focusing on Azure Cobalt. This hybrid role requires extensive experience in synthesis, place-and-route, timing, and physical verification, collaborating with cross-functional teams to optimize SOC blocks and deliver high-quality silicon solutions.

Responsibilities

Lead and execute end-to-end PD flow from synthesis through place-and-route for multiple designs, ensuring completion of all signoff stages including timing, physical verification, EMIR, formal equivalence, and low-power verification.
Responsible for clock construction and CTS.
Drive methodology exploration activities to optimize SOC blocks for clock construction and related methodology.
Coordinate with CAD, RTL/Design teams/DFT, Architecture team, Power & Performance team, Technology team & other internal/external partners.
Responsible for RTL to GDS implementation and ownership in Physical Design domain.
Influence design tools, flows, and methodologies in construction, signoff, and optimization through a data-driven approach.
Foster collaboration across teams to deliver the best possible solutions, aligned with a One Microsoft mindset.
Demonstrate leadership and technical expertise across various domains of Physical Design.
Clear communications on project status & planning.
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 7+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 10+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 12+ years technical engineering experience OR equivalent experience.
Track record in Physical Design domain implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
20+ years of experience in Physical design
Production silicon tape-outs experience in advanced foundry process nodes.
Experience in low power design methodology for SOC
Understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with various clock construction strategies for high speed designs
Demonstrate technical expertise in all aspects of Physical Design, from synthesis to place and route of partitions through all signoff including timing signoff, physical verification, EMIR signoff, Formal Equivalence, and Low Power Verification.
Own complete PD execution of medium to large-size SOC block. Be fully hands-on in technical domain ownerships as individual contributor and collaborate cross-team as required.
Partner closely with PD flow/CAD team and PD methodology team to flag & fix PD TFM issues
Problem-solving and data analysis skills
Ability to communicate effectively with cross-functional teams
Ability to meet Microsoft, customer and/or government security screening requirements.
Pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
Provide either proof of their country of citizenship or proof of their US. residency or other protected status for assessment of eligibility to access the export-controlled information.

Desired Qualifications

Experience in low power design methodology for SOC
Understanding of SOC or subsystem design trade-offs across power, performance, and area (PPA).
Familiarity with various clock construction strategies for high speed designs
Problem-solving and data analysis skills

Benefits

The typical base pay range for this role across the U.S. is USD $165,600 - $296,400 per year.
There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $220,800 - $331,200 per year.
Certain roles may be eligible for benefits and other compensation.
Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay.

Skills

SynthesisPlace and RouteTimingPhysical VerificationEMIRFormal EquivalenceLow-power VerificationClock ConstructionRTLGDSSOCPPA

#Hardware Engineering#Silicon Engineering#Cloud Infrastructure#Data Center#Chip Design#Manufacturing#Physical Design#SOC

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Company

Microsoft

Job Posted

2 days ago

Employment Type

Full Time

Work mode

Hybrid

Salary

US$165,600–296,400 · Negotiable

Experience Level

Senior

Locations

United States

Qualification

Doctoral, Master, Bachelor, No Formal Education

Applicants

Be an early applicant

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