CPU Hardware Verification (Power Management) Staff Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing

In short

Qualcomm is looking for a Staff Engineer in Bangalore, India, to lead the end-to-end verification of CPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features. This role requires deep expertise in SystemVerilog-based verification and power management validation, collaborating with cross-functional teams from architecture definition through signoff.

Responsibilities

Lead end-to-end verification of CPUCP/PDP firmware-driven hardware features, focusing on Power Management, Reliability, and System Readiness.
Architect and develop robust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructure for complex SoC subsystems.
Drive verification of AMBA-based system IPs including timers, mailbox, interrupts, and interconnect fabrics (NoC).
Own verification planning, test strategy, coverage modeling, coverage closure, and functional signoff.
Define and implement comprehensive validation for power-management features such as DVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences.
Lead complex debug and root-cause analysis across Firmware, RTL, Design, Emulation, and Post-Silicon teams.
Develop reusable stimulus frameworks, automation solutions, debug utilities, dashboards, and productivity tools.
Support platform bring-up, SoD readiness, feature qualification, HW/FW release validation, and silicon readiness activities.
Influence architecture reviews and verification methodologies, ensuring best practices are consistently applied.
Mentor junior engineers and foster a culture of technical excellence, ownership, and innovation.
Drive cross-functional initiatives spanning Firmware, Hardware Design, Emulation, and Post-Silicon Verification teams.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Extensive experience in SoC, CPU or Power-Management verification environments.
Strong expertise in SystemVerilog/UVM, verification methodologies, and testbench architecture.
Proven experience developing NoC transactors, protocol checkers, and verification infrastructure.
Deep understanding of AMBA protocols and system-level IPs such as timers, mailboxes, interrupts, and memory-mapped peripherals.
Strong background in RTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.
Experience validating power-management technologies including DVFS, LPM, idle states, power sequencing, and reset flows.
Proficiency in C/C++, SystemVerilog, Python, scripting, automation, and data-driven verification workflows.
Strong analytical and debugging skills with the ability to diagnose issues across HW, FW, and system domains.
Demonstrated ability to lead technical discussions, influence verification strategy, and drive execution across geographically distributed teams.

Desired Qualifications

10–12+ years of industry experience in CPU, GPU, SoC, or complex subsystem verification.
Proven expertise in pre-silicon verification methodologies, testbench architecture, and verification infrastructure development.
Strong track record of delivering verification signoff for complex SoC features from architecture definition through silicon bring-up.
Hands-on experience with automation frameworks, regression infrastructure, and CI/CD verification workflows.
Knowledge of system level Power management scenarios.
Previous experience mentoring engineers and leading cross team technical initiatives across organizations.
Added Advantage: Power Aware verification and Gate level simulation Hands – On experience