ASIC Physical Design, Staff Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Responsibilities
- Close timing on high performance memory IP including DDR, LPDDR, HBM, and SoC designs across multiple process corners and operating modes
- Own static timing analysis from constraint development through final signoff using PrimeTime, PTECO, and DMSA
- Debug and resolve complex timing violations including asynchronous domain crossings, multi-corner convergence issues, and setup/hold trade-offs
- Implement engineering change orders to fix functional bugs and timing failures without destabilizing already-closed paths
- Build and maintain automation scripts in Python, Perl, Tcl, and shell to streamline STA workflows, report generation, and ECO implementation
- Collaborate with physical design, RTL, and verification teams across global sites to ensure timing, power, and area requirements are met
- Drive quality and efficiency improvements in the RTL2GDS flow by identifying bottlenecks and proposing tooling or methodology changes
Requirements
- Bachelor's or Master's in Electronics Engineering, Electrical Engineering, Computer Science, or related field
- 5 to 9 years of hands-on experience in static timing analysis, with a focus on chip-level or IP-level timing closure
- Deep working knowledge of PrimeTime, PTECO, and distributed multi-scenario analysis tools
- Proven experience closing timing on high performance designs, ideally memory IP such as DDR, LPDDR, or HBM
- Strong scripting skills in Python, Tcl, Perl, or shell for automation and flow development
- Solid understanding of timing constraints, asynchronous timing analysis, and multi-corner/multi-mode closure strategies
Desired Qualifications
- Experience with physical design flows and RTL2GDS implementation is a strong plus
- You can look at a timing report with 500 violations and know within ten minutes which five actually matter and which are noise
- You push back when a constraint does not make sense or when an ECO will create more problems than it solves, and you do it with data, not opinion
- You write scripts that other engineers actually use because you think about maintainability and clarity, not just getting it done once
- You communicate timing issues to physical design teams and RTL engineers in terms they understand, without losing the technical nuance that matters for the fix
- You stay organized across multiple IPs, multiple corners, and multiple release schedules without dropping threads or missing deadlines
- You are comfortable working with global teams across time zones, and you know how to make asynchronous collaboration actually work
Benefits
- Competitive salaries
- Comprehensive medical and healthcare plans
- ETO and FTO Programs
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
- Retirement plans
Skills
Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…
Company
Synopsys IncJob Posted
3 days ago
Employment Type
Full Time
Work mode
On Site
Salary
Negotiable
Experience Level
Senior
Locations
Hyderabad, India
Qualification
Applicants
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