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Technical Architect

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

We are seeking a highly motivated Senior Memory Architect to design and optimize memory IPs such as SRAM, ROM, and Register files for advanced semiconductor nodes. The role involves transistor-level design, simulations using HSPICE/Spectre, and collaboration with cross-functional teams.

Responsibilities

  • Architect memory compiler and custom memory instance design.
  • Analyze memory specs and meet PPA requirements.
  • Perform transistor-level design and simulations (HSPICE, Spectre).
  • Conduct corner analysis, Monte Carlo simulations, and variation-aware design.
  • Debug design issues across PVT conditions.
  • Identify design margin measurements and create simulation setups.
  • Create and verify setups for Bitcell Analysis, Sense amp analysis, and self-time analysis.
  • Design and optimize leaf cells in memory from scratch.
  • Integrate leaf cells into memory instances and perform top-level simulations.
  • Manage multiple projects and guide team towards project closure.
  • Collaborate with layout and Verilog modelling teams.

Requirements

  • Good understanding of different Memory architectures (SRAM, ROM, emerging memory is a plus).
  • Familiar with bitcell and peripheral design.
  • Strong understanding of CMOS fundamentals.
  • Good understanding of Low-power design techniques.
  • Good understanding of various Read and Write assist circuits design techniques.
  • Good understanding of Redundancy and memory BIST feature.
  • Good Experience with Fast Spice and True Spice simulators.
  • Good understanding of critical path schematic creation for memory compiler modelling.
  • Good understanding of timing and power arcs required for memory characterization.
  • Good understanding of layout dependent effects in design.
  • Good understanding of parasitic extraction tool working and options associated with it.
  • Knowledge of memory compilers or embedded memory IP development.
  • Knowledge of FinFET technologies.
  • Exposure to ESPCV tool working.

Benefits

  • You'll supercharge your potential.
  • You'll find your career.
  • You'll find your spark.
  • A place that knows that helping its customers stay on top starts by putting its people first.

Skills

SRAMROMRegister filesHSPICESpectreCMOSLow-power designFinFETVerilog
#Memory Architect#semiconductor#memory IPs#SRAM#ROM#Register files#advanced semiconductor nodes#memory compiler#custom memory instance design#PPA#compiler design#transistor-level design#simulations#HSPICE#Spectre#corner analysis#Monte Carlo simulations#variation aware design#PVT conditions#design margin measurements#simulation setups#Bitcell Analysis#Sense amp analysis#self-time analysis#critical path schematic#leaf cells#memory instance#top level simulations#layout#Verilog modelling#Memory architectures#emerging memory#bitcell#peripheral design#CMOS fundamentals#Low-power design techniques#Read and Write assist circuits#Redundancy#memory BIST#Fast Spice#True Spice simulators#memory compiler modelling#timing and power arcs#memory characterization#layout dependent effects#parasitic extraction tool#embedded memory IP development#FinFET technologies#ESPCV tool
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About HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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Company

HCLTech

Job Posted

3 days ago

Employment Type

Full Time

Work mode

On Site

Experience Level

Senior

Locations

India

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