SOC Engineering, Sr Staff Engineer (STA)

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Synopsys seeks a Sr. Staff STA Engineer in Hyderabad, India to own and execute block-level STA signoff and contribute to full-chip timing closure for advanced nodes. The role involves debugging, developing constraints, power analysis, and supporting ECOs, requiring 8+ years of experience and proficiency in Synopsys tools and scripting languages like TCL and Python.

Responsibilities

Own and execute block-level STA signoff and contribute to full-chip timing closure for advanced process nodes.
Perform STA debugging and closure (setup/hold, recovery/removal, clock gating, CDC-related timing assumptions as applicable) and drive issue resolution with design/PD teams.
Develop, validate, and maintain timing constraints (SDC) including clocks, generated clocks, exceptions, IO constraints, and mode/corner coverage.
Run and analyze power signoff/support flows (PrimePower / PT-PX) and correlate timing/power impacts of ECOs.
Support timing and power ECO generation, and validate fixes through signoff checks and regressions.
Work with synthesis/implementation teams to ensure tool correlation and correct interpretation of constraints and physical effects (parasitics, SI awareness, AOCV/POCV, derates).
Use Synopsys tools such as PrimeTime, PrimePower/PT-PX, PrimeClosure/Tweaker (as applicable) to meet PPA targets.
Build/maintain automation in TCL/Python/Perl to improve STA productivity, reporting, and regression quality.
Contribute to improving STA methodologies, checklists, and best practices; mentor junior engineers informally as needed.

Requirements

Bachelor’s or Master’s degree (BE/BTech/MTech or equivalent) in Electronics/Electrical Engineering or related field.
8+ years of relevant experience in STA / timing closure (block ownership expected; full-chip exposure preferred).
Strong hands-on experience in: Constraints development/validation (SDC), STA signoff across modes/corners, including MMMC concepts, Timing closure debugging and ECO validation, Power analysis/support (PrimePower / PT-PX exposure preferred).
Proficiency with Synopsys tools such as PrimeTime (required); PrimePower/PT-PX, PrimeClosure/Tweaker (preferred).
Working knowledge/exposure to Fusion Compiler/ICC2 or DC, parasitic extraction concepts (e.g., StarRC), and signoff correlation (preferred).
Strong scripting skills in TCL (required) and Python/Perl (preferred).
Understanding of low-power and high-frequency design considerations (UPF awareness is a plus).

Desired Qualifications

Self-driven, accountable, and comfortable working with minimal supervision on defined deliverables.
Strong analytical and debugging skills with attention to detail.
Clear communicator and effective collaborator across design, PD, and verification.
Open to learning, improving flows, and sharing knowledge within the team.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP (Purchase Synopsys common stock at a 15% discount, with a 24 month look-back).
Retirement plans.
Competitive salaries.

Skills

TCLPythonPerlPrimeTimePrimePowerPT-PXPrimeClosureTweakerFusion CompilerICC2DCStarRCUPF

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About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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