SoC STA Engineer

Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering

In short

Qualcomm is looking for a SoC STA Engineer in Bangalore, India, to perform Static Timing Analysis (STA) setup, convergence, and signoff for complex designs. The role involves timing analysis, validation, debug, and automation scripting to optimize the STA flow and develop methodologies for various technology nodes.

Responsibilities

STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs.
Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.
Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation.
Evaluate multiple timing methodologies/tools on different designs and technology nodes.
Work on automation scripts within STA/PD tools for methodology development.
Technical writing and Communication skills, willingness to work in a cross-collaborative environment.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Experience in design automation using TCL/Perl/Python.
Familiar with digital flow design implementation RTL to GDS: ICC, Innovous, PT/Tempus.
Familiar with process technology enablement: Circuit simulations using Hspice/FineSim, Monte Carlo.

Desired Qualifications

5 - 10 years of experience in STA/Timing
Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling
Hands-on experience with STA tools - Prime-time, Tempus
Experience in driving timing convergence at Chip-level and Hard-Macro level
In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling
Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus)
Knowledge of Spice simulation Hspice/FineSim, Monte Carlo. Silicon to spice model correlation.
Proficient in scripting languages – TCL, Perl, Awk
Basic knowledge of device physics