Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet)

Technology, Data & Digital · Software & Web Development · Software Engineering · QA & Testing · Embedded Systems

In short

Synopsys is looking for a Senior Staff Interface IP Verification Engineer with extensive experience in pre-silicon verification of protocols like PCIe, CXL, DDR, and Ethernet. The role involves owning verification from architecture to signoff, building UVM environments, defining strategies, debugging complex issues, and mentoring junior engineers. This position is based in Munich and is not remote eligible.

Responsibilities

Own end-to-end verification of Interface IP blocks including PCIe, CXL, DDR, and Ethernet, from architecture review through silicon signoff
Build and evolve UVM-based verification environments that are reusable across product lines and scalable for future protocol generations
Define verification strategies and test plans that account for protocol compliance, performance corner cases, and system-level integration scenarios
Develop constrained-random, coverage-driven test scenarios using SystemVerilog and UVM, targeting functional coverage closure and signoff quality
Debug complex multi-layer issues spanning RTL logic, protocol state machines, timing, and testbench infrastructure using VCS or equivalent simulators
Collaborate with architecture, design, firmware, and systems teams to identify and resolve issues early in the development cycle
Mentor verification engineers on UVM methodology, coverage analysis, debugging techniques, and verification best practices

Requirements

Bachelor's or Master's in Electrical Engineering or Computer Engineering with 8+ years of hands-on ASIC or SoC verification experience
Deep expertise in SystemVerilog and UVM methodology, with a track record of building scalable verification environments from the ground up
Strong protocol knowledge in at least one of PCIe, CXL, DDR, or Ethernet, with the ability to read specs and translate them into verification requirements
Proven experience developing constrained-random and coverage-driven verification solutions that achieve functional signoff
Solid debugging skills across RTL, verification infrastructure, and protocol compliance, with experience using industry-standard simulators like VCS or ModelSim

Desired Qualifications

Experience with verification IP development, assertion-based verification, or formal methods is a strong plus
Knowledge of modern SoC architectures and high-speed communication interfaces is a plus

Benefits

Comprehensive medical and healthcare plans
ETO and FTO Programs (Time Away)
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans
Competitive salaries

Skills

PCIeCXLDDREthernetSystemVerilogUVMVCSModelSim

#Hardware Engineering#Semiconductor#Chip Architecture#Circuit Design#Verification#PCIe#CXL#DDR#Ethernet#Pre-Silicon#ASIC#SoC

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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