Senior Lead Post-Silicon validation Engineer - SMMU

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for a Senior Lead Post-Silicon Validation Engineer in Bangalore, India, to own the validation of System MMU (SMMU) blocks within complex SoCs. This role involves working with ARM-based architectures and ensuring functional correctness across pre-silicon and post-silicon phases.

Responsibilities

Own SMMU validation at block/IP and subsystem levels, including test planning, stimulus development, checking/score boarding, and closure.
Develop reusable verification components for SMMU, such as page table generators, translation fault injectors, and traffic generators.
Validate system interactions between SMMU and ARM cores, MMU/TLB, NoC/Interconnect, coherency, and clock/reset domains.
Exercise page table formats and features like stage-1/stage-2 translations, ASIDs/VMIDs, context banks/stream IDs, MSI/IOMMU operations, and address translation faults.
Debug complex issues using JTAG and on-chip debug/trace infrastructure, logic analyzers, and drive root cause analysis with design/architecture teams.
Perform performance and stress validation, measure bandwidth/latency, and validate backpressure & throttling behavior.
Contribute to emulation/FPGA and post-silicon activities, including porting tests, developing bare-metal validation, and creating board bring-up sequences and lab automation.
Own quality metrics like functional coverage, code coverage, assertions, and defect density/escape rates, authoring clear test/coverage reports and sign-off criteria.
Collaborate with architecture, RTL design, firmware/driver, physical design, and validation teams to refine specs and resolve issues.
Continuously improve methodology, tools, and checkers, and mentor junior engineers in best practices.

Requirements

B.E/B.Tech/M.Tech in ECE/EE/CS or equivalent with 3–5 years of relevant experience.
Strong ARM architecture knowledge (A-profile preferred), including memory model, privilege levels, exception model, caches, TLBs, MMU concepts, and virtual memory flows.
Deep understanding of SMMU/IOMMU fundamentals: stream IDs, context banks, translation stages, page table formats, fault handling, and device DMA interactions.
Familiarity with NoC/interconnect protocols and coherency (e.g., AXI/ACE/CHI), ordering rules, QoS, and interop with SMMU.
Solid grasp of clocks/resets and their impact on SMMU and NoC behavior; experience validating low-power states and clock gating effects.
JTAG basics to intermediate: scan chains, boundary scan, run-control, breakpoints, basic scripting with OpenOCD/DS-5/Arm Development Studio or similar.
Proficient in debugging complex HW/SW issues, using waveforms (e.g., Verdi/DVE), traces, and logs to isolate root cause.
Scripting in Python/Perl/TCL/Shell for test automation, log parsing, and lab workflows.
Critical thinking & learning agility: ability to infer failure modes from first principles, design edge-case tests, and quickly onboard new IP/flows.

Desired Qualifications

Prior tapeouts with SMMU or IOMMU IP (Arm SMMU v2/v3 or equivalent vendor IP).
Post-silicon validation experience: lab bring-up, firmware integration, board-level debug.
Experience with emulation/FPGA prototyping (Veloce, Palladium, Protium, HAPS).
Familiarity with Linux IOMMU framework, device trees/ACPI, and driver-level validation (DMA mappings, iommu_ops).
Knowledge of PCIe (including ATS/PRI/PASID), CXL, or virtualization stacks (KVM/Hypervisors) and their interaction with SMMU.
Exposure to safety/security: memory isolation, SMMU faults as security boundaries, RAS features, error injection and detection.
Performance modeling/analysis; profiling tools; building synthetic traffic to characterize SMMU/NoC behavior.
CI/CD for verification (Jenkins/GitLab CI), coverage dashboards, and regression triage at scale.

Benefits

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Qualcomm is committed to making its workplace accessible for individuals with disabilities.