NPU Staff Design Verification Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm seeks an experienced Staff Design Verification Engineer in Bangalore, India, to drive the verification of complex DSP/NPU IPs. Responsibilities include implementing System Verilog/UVM testbenches, developing new verification methodologies, and ensuring high-quality product releases. Requires 8+ years of experience in design verification of complex Qualcomm proprietary DSP/NPU IP.

Responsibilities

Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.
Implement and improve System Verilog/UVM Testbench Architecture.
Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.
Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.
Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.
Complete all required verification activities at IP level and ensure high quality commercial success of our products.
Utilize assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation on a daily basis.
Responsible for gate level simulation bring-up, gate level verification with timing simulations.
Responsible for power aware RTL verification and gate level simulation.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
8+ years of experience in design verification of complex Qualcomm proprietary DSP/NPU IP.
12+ years experience in processor/ASIC design verification.
Solid background and understanding of Digital Design, Processor Architecture, Processor Verification and Power aware verification.
Expertise in System Verilog Testbench Architecture and implementation.
Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence.
Scripting/Automation Skills — Perl, Python, Shell, Make file TCI.
Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.
Excellent inter-personal and communication skills.

Desired Qualifications

Experience in writing C based and assembly level testcases is preferred.
Exposure to power aware implementation and verification using UPF is a plus.
Experience with advanced verification techniques such as formal and assertions is a plus.
Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.
Experience in verification of Processor subsystems is preferred.
Experience in creating validation suite and building automation.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process.
Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process.
Qualcomm is also committed to making our workplace accessible for individuals with disabilities.