NPU Physical Design Engineer (Lead/Staff/Sr Staff)

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Qualcomm seeks a NPU Physical Design Engineer in Bangalore, India, to lead PNR implementation for Qualcomm Hexagon NPU. This role requires expertise in Floorplanning, PNR, STA flows, and signoff domains on latest nodes.

Responsibilities

PNR implementation for Qualcomm Hexagon NPU
Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post-route,etc) on latest nodes.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Good hands-on experience on Floorplanning, PNR and STA flows
Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc
Good understanding on signoff domains– LEC/CLP/PDN knowledge, etc
Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting
Signoff knowledge is mandatory (STA,Power analysis,FV, low power verification, PV,etc)
7+ years experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm)