NPU Design Verification Sr Lead Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering

In short

Position for an experienced NPU Design Verification Sr Lead Engineer in Bangalore, India, to drive the verification of complex DSP/NPU IP. This role involves implementing and improving System Verilog/UVM Testbench Architecture, developing new verification methodologies, and ensuring high-quality commercial success of products through hands-on simulation and debugging at IP, Subsystem, and SoC levels.

Responsibilities

Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams.
Implement and improve System Verilog/UVM Testbench Architecture.
Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency.
Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals.
Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs.
Complete all required verification activities at IP level and ensure high quality commercial success of our products.
Utilize assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation on a daily basis.
Responsible for gate level simulation bring-up, gate level verification with timing simulations.
Responsible for power aware RTL verification and gate level simulation.

Requirements

5+ years of experience in design verification of complex Qualcomm proprietary DSP/NPU IP.
2+ years experience in processor/ASIC design verification.
Solid background and understanding of Digital Design, Processor Architecture, Processor Verification and Power aware verification.
Expertise in System Verilog Testbench Architecture and implementation.
Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence.
Scripting/Automation Skills — Perl, Python, Shell, Make file TCI.
Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts.
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Desired Qualifications

Experience in writing C based and assembly level testcases is preferred.
Exposure to power aware implementation and verification using UPF is a plus.
Experience with advanced verification techniques such as formal and assertions is a plus.
Gate-Level Simulation and Debug — 0-delay, timing annotated and power aware.
Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred.
Experience in verification of Processor subsystems is preferred.
Experience in creating validation suite and building automation.
Excellent inter-personal and communication skills.

Benefits

Qualcomm is an equal opportunity employer, committed to providing an accessible process for individuals with disabilities.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.