Tech IP Library Characterization Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · Inbyggda system

I korthet

We are seeking an ambitious Tech IP Library Characterization Engineer to join our TECHIP team in Tijuana. The role requires strong IP modeling, characterization tool know-how, and hands-on experience in EDA tool automation, data analysis, and large-scale software automation. The ideal candidate will have excellent understanding of statistical Liberty timing and power models, along with Front-end Verilog views and tools.

Ansvarsområden

IP modeling, Char tool know-how and hands-on experience and automation skills
Hands-on experience in EDA tool automation, data analysis and visualization & large-scale software automation enablement
Drive cutting edge tools, flows in QCOM environment for characterization flow and sign-off methodologies

Krav

Strong Std cell / Memory circuit knowledge & IP characterization, Design Kit delivery background
Strong logical and problem-solving skills with excellent analytical and debugging skills
Strong Software programming skills in Python or Perl in UNIX/Linux computing platform
Highly motivated, excellent team spirit and good communication skills
Ability to work in multi-site project teams, third party vendors

Önskade kvalifikationer

In depth technical knowledge of CMOS, FinFET logic and transistor, basic of digital circuit design optimization
Familiar with industry standard Design kit (DK) views, Liberty formats for foundation IPs (advanced modeling formats CCS, LVF) , statistical variation models & worked on development of the same
Familiarity with front end pre-silicon design flow, RTL design/coding, logic design, Verilog/ System Verilog, RTL design verification, System Verilog Assertion (SVA), Design for Test, BIST modeling experience
Expertise in scripting in Python (data-analytics), Perl & experience in developing large scale automation from scratch
Experience in STA, physical design is a plus
Experience of spice simulation models, design rules verification procedures (like DRC/LVS/ERC) is a plus
Experience with industry standard chip design tools and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power Analysis

Färdigheter

PythonPerlVerilogSystem VerilogSVADRCLVSERCSTASpice

#IP#Library#Characterization#EDA#automation#data analysis#visualization#Python#Perl#UNIX#Linux#CMOS#FinFET#digital circuit design#Design Kit#Liberty formats#foundation IPs#CCS#LVF#statistical variation models#RTL design#logic design#RTL design verification#SVA#DFT#BIST modeling#STA#physical design#Spice simulation#DRC#LVS#ERC#chip design tools#design flows#Static Timing Analysis#Fast spice simulation#Synthesis#DFT#Power Analysis