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Staff design Verification Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling · QA och testning

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Qualcomm is looking for a Staff Design Verification Engineer in Noida, India, to join their ASIC Engineering group. The role involves pre-Si validation for DDRSS IP, requiring expertise in UVM, System Verilog, and bus protocols, with a minimum of 8 years of experience.

Ansvarsområden

  • Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high-performance products.
  • Collaborate with cross-functional groups to determine product execution path.
  • Develop test-bench / DV environment, think out-of-the-box to break the design.
  • Explore and develop new technologies to make the validation process more robust.
  • Expertise of DDRSS DV test bench and other associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage).
  • Planning & execution of feature additions and mode re-enablement on particular variants.
  • Debug of regression signatures and identifying bug fixes.
  • Developing/Deploying new tools for validation (Certitude, VC Formal, Fishtail).
  • Working with all stakeholders to ensure program success.

Krav

  • Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
  • Minimum 8+ years of experience.
  • Thorough understanding of Digital design concepts.
  • Strong Debug, UVM, System Verilog.
  • Understanding of Bus protocols like AHB/AXI/ACE/ACE-Lite.
  • Understanding of multi-core ARMv8 CPU architecture, coherency protocols and virtualization.
  • Good understanding of DDR families (LP/PC) and generations (DDR2/3/4/5).
  • Quick understanding of Specs and Standards and developing relevant and thorough test plans.
  • Experience with monitors, scoreboards, sequencers and sequences, that utilize scripts, System Verilog, UVM, and methodologies to increase the rate with which bugs are found and resolved.
  • Comfortable checking builds, navigating big test benches, analyzing coverage, and adding or enabling extra debug.
  • Willing to dig into fails and understand what is happening.

Önskade kvalifikationer

  • Post-Si bring-up and HW-SW debug experience would be a plus.
  • Knowledge & exposure to silicon debug tool chains would be an added advantage.
#ASIC#Design Verification#Hardware Engineering
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Företag

Qualcomm

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Noida, India

Kvalifikation

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