SoC RTL Design Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Qualcomm Vietnam seeks an SoC RTL Design Engineer for complex SoC and subsystem integration. Responsibilities include RTL integration, design quality assessment, synthesis, and front-end readiness for downstream implementation and verification, working with global teams. Ideal candidates will have a Bachelor's degree, 3+ years of experience in RTL design, SoC integration, or synthesis, and proficiency in Verilog/SystemVerilog and front-end design flows.

Ansvarsområden

Integrate RTL from multiple IPs, subsystems, and reusable design components into SoC-level and subsystem-level designs.
Develop and maintain top-level RTL wrappers, hierarchy, interconnect, connectivity, clock and reset structures, interrupt paths, and configuration logic.
Work with standard SoC interfaces and protocols, including AXI, AHB, APB, memory, debug, interrupt, clock, reset, and power-management interfaces.
Coordinate IP releases, integration dependencies, file lists, manifests, parameters, build configurations, and design collateral.
Run and debug RTL compile/elaboration, lint, CDC, RDC, structural checks, formal connectivity, and synthesis flows.
Prepare RTL, constraints, libraries, and configuration inputs for synthesis and downstream physical implementation.
Analyze synthesis reports for timing, area, power, high-fanout, unmapped logic, inferred structures, unconnected signals, and design-rule issues.
Collaborate with physical design teams to resolve critical paths, timing-convergence issues, congestion risks, and implementation constraints.
Support functional equivalence, gate-level simulation, emulation, FPGA, ECO, and design-release readiness activities.
Investigate failures across RTL, tools, constraints, configuration, and build environments; identify root cause and drive corrective action.
Participate in design reviews, code reviews, integration reviews, methodology improvements, and technical documentation activities.

Krav

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
3+ years of relevant work experience in RTL design, SoC integration, synthesis, ASIC/FPGA development, or a related area.
Experience with Verilog or SystemVerilog RTL development and hierarchical design integration.
Experience with RTL simulation, compilation/elaboration, lint, CDC/RDC, synthesis, or equivalent front-end design flows.
Knowledge of digital design fundamentals, timing concepts, clock/reset design, bus protocols, and hardware/software interfaces.
Ability to analyze technical problems, communicate root cause clearly, and work effectively in a distributed, cross-functional team.

Önskade kvalifikationer

Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Experience integrating complex SoCs, subsystems, infrastructure IP, NoC/interconnect, memory, debug, security, or power-management logic.
Hands-on experience with synthesis, timing constraints, timing analysis, area/power optimization, formal equivalence, ECO, or gate-level simulation.
Experience with low-power design concepts, power intent, isolation, retention, multi-voltage design, clock-domain crossings, or reset-domain crossings.
Experience with Python, Perl, Tcl, Shell, or similar scripting for flow automation, quality checks, reporting, and build management.
Experience with internal or commercial EDA tools for simulation, lint, CDC, synthesis, formal verification, and implementation handoff.
Knowledge of SoC release QA, connectivity signoff, design documentation, and reusable IP/subsystem delivery processes.
Self-motivated, detail-oriented, and comfortable taking ownership of ambiguous technical problems across organizational boundaries.