Senior Solution Architect

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Senior Solution Architect to lead technical interfaces between semiconductor design and foundries, covering technology selection, manufacturing, and yield. This role requires deep understanding of ASIC/SoC development and direct experience with major foundries.

Ansvarsområden

Act as the primary technical interface with the foundry for assigned semiconductor programs.
Drive technology and process selection based on performance, power, area, reliability, cost, and product requirements.
Coordinate PDK, technology collateral, design rules, standard-cell libraries, and process documentation required by design teams.
Manage foundry engagement for wafer fabrication, tapeout, mask release, wafer schedules, and silicon delivery.
Work closely with RTL, physical design, DFT, STA, reliability, packaging, and product engineering teams to resolve foundry-related issues.
Drive DRC/LVS/PEX and manufacturing-rule closure in collaboration with design and foundry teams.
Coordinate foundry reviews for signoff, tapeout, mask data preparation, and manufacturing readiness.
Track wafer fabrication status, engineering lots, process milestones, and first-silicon delivery.
Establish and maintain foundry technical governance, escalation mechanisms, and issue-tracking processes.
Support commercial and capacity discussions with the foundry in coordination with procurement and business teams.
Ensure compliance with foundry NDA, IP, security, and technology-access requirements.
Maintain risk registers covering technology maturity, PDK readiness, wafer capacity, yield, schedule, and manufacturing risks.

Krav

Strong understanding of ASIC/SoC development and semiconductor manufacturing flows.
Strong understanding of PDK and technology enablement.
Strong understanding of Design rules.
Strong understanding of DRC/LVS.
Strong understanding of Physical design and signoff.
Strong understanding of Tapeout and mask data preparation.
Strong understanding of Wafer fabrication.
Strong understanding of Wafer sort.
Experience working directly with major foundries such as TSMC, Samsung Foundry, GlobalFoundries, UMC, or equivalent.
Experience with advanced-node and/or mature-node semiconductor technologies.
Good understanding of PVT/process corners, reliability, electromigration, IR drop, process variation, and manufacturing variability.
Ability to understand, coordinate, and resolve technical issues across semiconductor design and manufacturing teams.
Strong experience leading cross-functional semiconductor engineering teams.
Ability to work with foundry technical teams at both engineering and management levels.
Strong communication and escalation-management skills.
Ability to drive complex technical issues to closure across multiple organizations.
Ability to manage multiple semiconductor programs and competing priorities.
Strong stakeholder-management and relationship-building capabilities.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Microelectronics, VLSI, Semiconductor Engineering, or a related field.
12–20 years of experience in semiconductor/ASIC/SoC development, with significant experience interfacing with semiconductor foundries.
Proven experience taking multiple silicon programs from technology selection/PDK enablement through tapeout, wafer fabrication, and first silicon.
Strong knowledge of foundry processes, PDKs, design rules, physical design, DRC/LVS, STA, tapeout, wafer fabrication, yield, and silicon characterization.
Direct experience working with one or more major foundries such as TSMC, Samsung Foundry, GlobalFoundries, UMC, or equivalent.
Demonstrated ability to lead cross-functional technical teams and manage technical escalations with foundry engineering teams.
Strong understanding of semiconductor manufacturing risks, including process variation, yield, reliability, wafer quality, and manufacturing readiness.
Excellent technical communication, stakeholder management, problem-solving, and negotiation skills.

Önskade kvalifikationer

Experience with advanced-node technologies and/or complex SoC/ASIC programs is preferred.
Exposure to chiplet, 2.5D/3D packaging, automotive semiconductor, AI/HPC, networking, or high-performance silicon programs is an advantage.

Förmåner

Consolidated revenues as of 12 months ending September 2026 totaled $14.8 billion.

Färdigheter

PDKDRC/LVSPhysical DesignTapeoutWafer FabricationTSMCSamsung FoundryGlobalFoundriesUMCSoCASIC

#Solution Architect#Semiconductor#Foundry#ASIC#SoC#PDK#DRC/LVS#Physical Design#Tapeout#Wafer Fabrication

Om HCLTech

Supercharging progress through technology and innovation

HCLTech is a global technology company, home to 219,000+ people across 54 countries, delivering industry-leading capabilities centered around digital, engineering and cloud, powered by a broad portfolio of technology services and products. We work with clients across all major verticals, providing industry solutions for Financial Services, Manufacturing, Life Sciences and Healthcare, Technology and Services, Telecom and Media, Retail and CPG, and Public Services. Consolidated revenues as of 12 months ending September 2022 totaled $12.1 billion. To learn how we can supercharge progress for…

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Senior

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Bangalore, India

Chennai, India

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Kandidatexamen, Masterexamen

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