Senior FPGA Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

I korthet

Synopsys seeks an experienced Senior FPGA Engineer to join their team in Moreira, Portugal. This role involves designing, verifying, and optimizing high-performance PCIe-based FPGA solutions from architecture to hardware bring-up, contributing to advanced semiconductor development.

Ansvarsområden

Prototype and optimize high-performance PCIe-based designs on FPGA platforms using Vivado, driving the implementation flow through synthesis, place and route, timing closure, and hardware bring-up
Simulate and verify PCIe-based prototype designs using industry-standard verification methodologies such as UVM, ensuring correct functionality and behavior prior to FPGA implementation and hardware bring-up
Perform timing analysis and optimization across multiple clock domains, resolving setup and hold violations and ensuring designs meet performance targets
Collaborate with hardware, software, and verification teams to define requirements, evaluate design tradeoffs, and deliver FPGA solutions that meet project goals
Develop and execute test plans to validate functionality, performance, and reliability of FPGA prototypes in real-world conditions
Participate in industry events, including PCI-SIG Compliance Workshops, to perform official compliance testing of PCIe prototypes and ensure conformance with applicable PCIe specifications and industry standards
Debug and resolve hardware, protocol, and system-level issues identified during PCIe compliance testing, working across the FPGA prototype and test environment to achieve successful compliance results

Krav

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent hands-on experience
Ideally 8+ years of FPGA design and development experience, with a strong track record of shipping working designs
Deep proficiency in Verilog and RTL design, including experience with complex state machines, pipelines, and multi-clock domain architectures
Strong command of Vivado or similar FPGA toolchains, including synthesis, implementation, and timing closure workflows
Solid understanding of digital design fundamentals: clock domain crossings, metastability, timing constraints, and static timing analysis
Experience with high-speed interfaces such as PCIe or Ethernet, including protocol-level understanding and debug

Önskade kvalifikationer

Experience with scripting languages like Python or Tcl for automation and tooling is a plus

Förmåner

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
ESPP (Synopsys common stock at a 15% discount)
Retirement Plans
Competitive salaries

Färdigheter

VerilogVivadoPCIeUVMPythonTcl

#FPGA#PCIe#EDA#RTL#Vivado#UVM#timing closure#hardware validation#compliance testing#Verilog#semiconductor

Om Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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