Lead engineer Pre-Silicon System Performance

Teknik, data och digitalt · IT-infrastruktur och säkerhet · Systemteknik

I korthet

The Senior Staff Engineer will lead end-to-end system performance strategy, methodology, and sign-off for complex server-class SoCs. This role requires deep expertise in SoC micro-architecture, memory systems, and interconnects, influencing architecture and design decisions. Responsibilities include owning system-level performance, defining methodologies, leading investigations, and mentoring engineers.

Ansvarsområden

Own system-level performance sign-off across multiple subsystems and use cases.
Define and drive performance methodology and benchmarks for pre-silicon and early silicon platforms.
Lead deep-dive investigations involving CPU, memory, NoC, IO, and power-performance trade-offs.
Translate architecture features into quantitative performance projections and risks.
Influence architecture and design trade-offs.
Mentor engineers and act as a technical authority.
Works independently with significant impact on product performance and program success.

Krav

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
10+ years of industry experience in SoC/System performance, architecture, or validation.
Strong expertise in SoC micro-architecture, memory systems, and interconnects.
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 6+ years of Systems Engineering or related work experience.
OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 5+ years of Systems Engineering or related work experience.
OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.

Önskade kvalifikationer

Master’s degree or PhD (or equivalent experience).
Extensive experience with RUMI/emulation-based performance sign-off.
Preferred experience in Server-class / Data Center SoC architecture, including cache-coherent interconnects (e.g., CHI/ACE-class fabrics), scalable memory hierarchies, and high-bandwidth IO subsystems (PCIe/CXL-class), with ability to translate architecture features into performance sign-off metrics and system-level debug.

Färdigheter

SoCSystem performanceCPUmemoryNoCIOpower-performanceperformance projectionsarchitectureElectrical EngineeringComputer EngineeringComputer Sciencemicro-architecturememory systemsinterconnectsRUMIemulationcache-coherent interconnectsPCIeCXL

#System Performance#SoC#Pre-Silicon#Performance Engineering#Server SoC#Architecture