The Job

DDR/LPDDR IP Design Principal Engineer

Teknik, data och digitalt · Mjukvaru- och webbutveckling · Mjukvaruutveckling

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I korthet

Synopsys is seeking a Principal Engineer for their DDR/LPDDR IP Design team in Wuhan, China. The role involves designing and verifying cutting-edge semiconductor solutions, with a focus on ASIC design methodology and debug skills. Experience with Verilog, System Verilog, and EDA tools is required.

Ansvarsområden

  • Work on digital design based on predefined RTL coding style include Verilog and System Verilog.
  • Clean RTL check violations in lint, CDC, DFT and synthesis.
  • Solid Debugging skills and ability to root cause issues include both simulation and silicon.
  • Interact with Application Engineers for customer support.

Krav

  • BSEE in EE with 12+ years of digital design experience or MSEE with 9+ years of relevant experience.
  • Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality.
  • Good communication skills for interacting between different design groups and customer support teams are required.

Önskade kvalifikationer

  • Theoretical and practical background in DDR or LPDDR is a solid plus.
  • Has strong desire to learn and explore new technologies.
  • Demonstrates good analysis and problem-solving skills.
  • Knowledge in interface technologies such as DDR, HBM, UCIe is a plus.
  • Scripting experience in Shell, Perl, Python and TCL is a plus.
  • Knowledge of analogic circuit is a plus.

Förmåner

  • Comprehensive medical and healthcare plans that work for you and your family.
  • In addition to company holidays, we have ETO and FTO Programs.
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
  • Save for your future with our retirement plans that vary by region and country.
  • Competitive salaries.
#DDR#LPDDR#IP Design#Principal Engineer#ASIC#RTL#Verilog#System Verilog#Debugging#Simulation#Silicon Debug#VCS#Verdi#Spyglass#DC#Formality#EDA Tools
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Företag

Synopsys Inc

Publicerade jobb

för 1 vecka sedan

Anställningstyp

Heltid

Arbetsform

På plats

Erfarenhetsnivå

Senior

Platser

Wuhan, China

Kvalifikation

Kandidatexamen, Masterexamen

Sökande

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