DDR/LPDDR IP Design Principal Engineer
Technology, Data & Digital · Software & Web Development · Software Engineering
In short
Synopsys is seeking a Principal Engineer for their DDR/LPDDR IP Design team in Wuhan, China. The role involves designing and verifying cutting-edge semiconductor solutions, with a focus on ASIC design methodology and debug skills. Experience with Verilog, System Verilog, and EDA tools is required.
Responsibilities
- Work on digital design based on predefined RTL coding style include Verilog and System Verilog.
- Clean RTL check violations in lint, CDC, DFT and synthesis.
- Solid Debugging skills and ability to root cause issues include both simulation and silicon.
- Interact with Application Engineers for customer support.
Requirements
- BSEE in EE with 12+ years of digital design experience or MSEE with 9+ years of relevant experience.
- Good knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality.
- Good communication skills for interacting between different design groups and customer support teams are required.
Desired Qualifications
- Theoretical and practical background in DDR or LPDDR is a solid plus.
- Has strong desire to learn and explore new technologies.
- Demonstrates good analysis and problem-solving skills.
- Knowledge in interface technologies such as DDR, HBM, UCIe is a plus.
- Scripting experience in Shell, Perl, Python and TCL is a plus.
- Knowledge of analogic circuit is a plus.
Benefits
- Comprehensive medical and healthcare plans that work for you and your family.
- In addition to company holidays, we have ETO and FTO Programs.
- Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
- Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
- Save for your future with our retirement plans that vary by region and country.
- Competitive salaries.
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