ASICS Design Verification Engineer - Multiple levels

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I korthet

Qualcomm is seeking an ASICS Design Verification Engineer in Vancouver, BC, responsible for the complete verification lifecycle of digital power IPs. This role involves pre-silicon test planning, testbench development, coverage, and formal verification, requiring a Bachelor's or Master's degree and relevant experience.

Ansvarsområden

Responsible for the complete verification lifecycle, from system-level concept to tape out and post-silicon support.
Comprehensive pre-silicon test planning for digital power IP's.
Testbench development using advanced verification methodologies such as SystemVerilog-UVM.
Coverage development and assertion model development.
Involvement in formal verification (property checking).
Learn and deploy power-aware UPF verification flow and methodology.
Develop automation to improve verification efficiency.

Krav

Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.
Experience with ASIC design and verification tools, techniques, and methodology.
Experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
Experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
Experience with developing block-level testbench environment using SystemVerilog.
Experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
Experience with scripting/automation skills using either Perl or python.

Önskade kvalifikationer

Master’s degree in Computer Science, Electrical Engineer, Computer Engineering, or a closely related field.
6+ years of experience with ASIC design and verification tools, techniques, and methodology.
6+ years of experience with digital design concepts and RTL languages such as SystemVerilog or Verilog, or VHDL.
6+ years of experience with computer architecture fundamentals, Object-oriented programming concepts and C or C++ programming skills.
6+ years of experience with developing block-level testbench environment using SystemVerilog.
6+ years of experience with verification methodologies through coursework or past experiences such as UVM or OVM and exposure to Assertion based Formal Verification.
6+ years of experience with scripting/automation skills using either Perl or python.
Experience with AMBA Bus protocol (AXI/AHB/APB etc) is desirable (not mandatory).
Knowledge or experience with Assertion Based Formal Verification is desirable (not mandatory).

Förmåner

Competitive annual discretionary bonus program.
Opportunity for annual RSU grants.
Highly competitive benefits package designed to support success at work, at home, and at play.
Qualcomm is an equal opportunity employer.
Commitment to providing an accessible process for individuals with disabilities.
Reasonable accommodations to support individuals with disabilities to participate in the hiring process.
Commitment to making the workplace accessible for individuals with disabilities.

Färdigheter

SystemVerilogUVMVerilogVHDLC++PerlPythonAXIAHBAPB

#ASICS#Design Verification#Engineering#Qualcomm

Om Qualcomm

Enabling a world where everyone and everything can be intelligently connected.

Enabling a world where everyone and everything can be intelligently connected.\n\n

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Företag

Qualcomm

Publicerade jobb

för 3 veckor sedan

Anställningstyp

Heltid

Arbetsform

På plats

Lön

108 000–158 000 US$ / år

Erfarenhetsnivå

Mellannivå

Platser

Vancouver, Canada

Kvalifikation

Kandidatexamen, Masterexamen, Doktorand

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