ASIC Digital Design, Principal Engineer-18731

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I korthet

Principal Engineer in ASIC Digital Design at Synopsys, Mississauga, Ontario. This role focuses on designing and developing cutting-edge semiconductor solutions, specifically high-speed silicon IP with a focus on PCIe PHY technology. The ideal candidate has extensive experience in ASIC verification, including mixed-signal IP, PCIe PHY architectures, and modern verification methodologies.

Ansvarsområden

Define and drive the verification strategy and functional quality for next-generation PCIe PHY IPs.
Develop comprehensive verification plans for complex mixed-signal digital designs with primary emphasis on PCIe PHY functionality and protocol compliance.
Architect, develop, and execute advanced testbench environments for block-level and subsystem-level verification.
Verify key PCIe PHY features such as LTSSM behavior, PIPE interface interactions, link initialization and training, power management, equalization flows, error handling, and compliance-related scenarios.
Work closely with design, analog, firmware, architecture, and validation teams to ensure robust coverage of cross-functional use cases.
Use advanced verification methodologies, including constrained-random, assertion-based verification, coverage-driven verification, and debug automation, to achieve high-quality results.
Analyze failures, root-cause complex issues, and drive resolution across design and verification domains.
Mentor and guide other engineers, promote verification best practices, and help build a culture of technical excellence and continuous improvement.
Communicate effectively with internal stakeholders and customers to align on technical goals, verification quality, and deliverables.

Krav

Extensive experience in mixed-signal ASIC/IP verification.
Strong expertise in PCIe and PCIe PHY verification.
Solid understanding of high-speed SerDes/PHY architecture and digital control verification in mixed-signal environments.
Hands-on experience with modern verification methodologies such as SystemVerilog, UVM, assertions, and coverage-driven verification.
Experience developing verification plans, building reusable verification environments, and closing coverage for complex IP products.
Strong debugging and problem-solving skills, with the ability to work independently and drive issues to closure.
Excellent communication and collaboration skills for working across global, cross-functional teams.
Proven ability to mentor engineers and lead technical verification activities.

Önskade kvalifikationer

A technical leader who can drive verification excellence for complex PCIe PHY IP products.
A mentor who develops talent, shares knowledge, and raises the bar for the team.
A proactive problem solver who thrives in technically challenging environments.
A strong communicator who can clearly convey complex concepts to both technical and cross-functional audiences.
A collaborative team player who values innovation, quality, and execution.

Förmåner

Comprehensive medical and healthcare plans.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement Plans.
Competitive salaries.

Färdigheter

PCIe PHYmixed-signalSystemVerilogUVMSerDes

#Digital Design#Engineering#ASIC#Principal Engineer

Om Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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