Analog / Mixed-Signal SerDes Design Engineer

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I korthet

QT Technologies Ireland Limited is seeking an Analog/Mixed-Signal SerDes Design Engineer in Cork, Ireland to work on high-speed PHY receivers and drivers for advanced SoC products. The role involves custom circuit design, simulation, verification, and integration in leading-edge FinFET and GAA process nodes.

Ansvarsområden

Architecture, design, and development of analog/mixed signal hard macros for the SerDes IP Design team.
Perform custom circuit design in the latest FinFET CMOS processes technologies and beyond to support the delivery of SerDes IP.
Participate in internal customer requirements discussions.
Create design specifications.
Create behavioral models in Verilog.
Set-up, run and analyze circuit simulations.
Perform quality assurance procedures on developed hard macros.
Deliver hard macros and support customer integration and testing.
Perform silicon characterization analysis and prepare silicon verification reports.

Krav

Master’s or Ph.D. degree in Science, Engineering, or related field.
A minimum of 3-years of transistor level analog mixed-signal design experience, preferably in high-speed wireline SerDes, PLL, DDR or other high speed applications.
Experience in SPICE simulators and schematic capture tools.
Experience in designing op-amps, bandgaps, differential amplifiers, VCO, PLL, DLL.
Experience in high-speed SerDes block level designs such as transmitters, receivers, high speed VGA, CTLE, CDR, etc.
Understanding of signal integrity in high-speed wireline design is preferred.
Scripting to automate circuit design and verification work.
Full-custom analog layout techniques and the ability to take a design and do all the layout extract verification and sign-off.
Excellent communication skills and ability to contribute strongly within a high-performance team.

Önskade kvalifikationer

Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field.