Staff Engineer – STA Methodology/CAD

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking a Staff Engineer – STA Methodology in Bangalore, India, to lead the development and enhancement of Static Timing Analysis (STA) methodologies for complex SoCs. This role involves driving timing signoff, developing automation with Tcl/Python, and collaborating with cross-functional teams on timing closure and advanced techniques.

Responsibilities

Define, develop, and improve STA methodologies for block, subsystem, and full-chip designs.
Drive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies.
Develop automation and infrastructure using Tcl/Python/Perl to improve timing analysis efficiency and turnaround time.
Own methodology development for timing closure, reporting, constraint management, and signoff quality metrics.
Collaborate closely with RTL, Synthesis, Physical Design, DFT, and CAD teams to enable robust timing convergence.
Drive adoption of advanced timing techniques including SOCV/AOCV, hierarchical STA, and signoff optimization flows.
Debug complex timing issues and provide scalable solutions across multiple projects.
Evaluate and deploy new EDA tool capabilities and AI-driven timing closure methodologies.
Mentor junior engineers and provide technical leadership across STA methodology initiatives.

Requirements

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.
Strong understanding of Static Timing Analysis (STA).
Strong understanding of MMMC timing signoff.
Strong understanding of Timing constraints (SDC).
Strong understanding of Setup/Hold closure methodologies.
Strong understanding of SOCV/AOCV derates.
Strong understanding of ECO and timing convergence techniques.
Expertise with Synopsys PrimeTime or Cadence Tempus.
Strong scripting skills in Tcl and Python.

Desired Qualifications

Experience with advanced technology nodes (7nm and below).
Experience developing timing automation frameworks, dashboards, and reporting infrastructure.
Knowledge of Synthesis, Physical Design, DFT, and power-aware timing analysis.
Exposure to AI/ML-driven timing optimization and methodology development.
Proven track record of driving methodology improvements adopted across multiple programs.
Strong communication, collaboration, and technical leadership skills.