Master Thesis: Learned Evidence Ranking for ASIC Verification Quality and Debug using AI ML

Technology, Data & Digital · Software & Web Development · Software Engineering · Machine Learning · Data Engineering

In short

This Master Thesis focuses on developing an AI/ML-driven system to automate failure diagnosis and assess testbench quality in ASIC verification. You will work with real production data to learn how to rank diagnostic events, reducing manual log inspection time and gaining valuable skills in hardware verification and machine learning.

Responsibilities

Build a data-driven framework for automated failure diagnosis and testbench quality assessment.
Capture and correlate relevant verification events beyond conventional UVM messages.
Train and evaluate a model that ranks events by diagnostic relevance.
Compare the results with expert engineer assessments and manual triage effort.
Develop a prototype for auditable testbench quality scoring.
Explore whether failure patterns can be detected before an error appears (optional stretch goal).

Requirements

Master´s student in electrical or computer engineering, computer science, embedded systems, or a similar field.
Knowledge of computer architecture, ASIC design and RTL/HDL coding.
Experience with SystemVerilog and testbench design.
Scripting experience, preferably Tcl or Python, for EDA tools.
Fundamentals of artificial intelligence and machine learning.
Exposure to at least one AI/ML model architecture, from data preparation through evaluation.
An analytical and research-oriented mindset.
Interest in verification, observability and data-driven engineering.

Desired Qualifications

Working knowledge of UVM is preferred.

Benefits

A rare combination of hardware verification and machine-learning skills, increasingly in demand across the semiconductor industry.
End-to-end ML experience on real production data from raw data to rigorous evaluation.
Insight into how large chips are verified and where the hardest problems lie.
Mentorship from experienced verification engineers at Ericsson, with access to real tools and data.

Skills

PythonTclSystemVerilogAIML

#ASIC#Verification#AI#ML#Master Thesis

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