ASIC Physical Design, Manager

Construction, Engineering & Trades · Civil & Industrial Engineering · Electrical Engineering

In short

Synopsys is looking for an experienced ASIC Physical Design Manager to lead a team in Bengaluru, Karnataka, India. The role involves driving end-to-end execution of testchip projects, managing timing closure, power optimization, and physical verification, while also mentoring engineers and improving design automation flows.

Responsibilities

Lead a team of physical design engineers responsible for building and maintaining the complete PD flow and methodology for the Testchip team, from RTL handoff through GDSII delivery
Drive end-to-end execution of multiple testchip projects, managing timing closure, power optimization, and physical verification using tools like ICC2, Fusion Compiler, PrimeTime, and Calibre
Set up and continuously improve design automation flows across physical design stages, including scripting for repeatability, quality checks, and faster closure cycles
Collaborate with front-end design, silicon validation, and software teams to align on design intent, verify handoffs, and troubleshoot issues that span multiple domains
Manage project schedules, resource allocation, and risk mitigation to hit tape out dates while maintaining quality and design robustness
Serve as the technical point of contact for foundry interactions, translating foundry requirements into actionable design constraints and managing DRC/LVS closure
Mentor engineers on timing analysis, floorplanning, place and route strategies, and verification best practices, building depth and judgment across the team

Requirements

8 to 14 years of hands-on experience in ASIC physical design, with at least 2 years leading teams or managing projects
Proven track record of multiple successful tape outs, ideally across different process nodes or design complexities
Deep expertise in physical design implementation, timing closure, power optimization, and physical verification using industry-standard EDA tools like Fusion Compiler, ICC2, PrimeTime, Tempus, Calibre, or equivalent
Strong understanding of the complete chip design flow from RTL to GDSII, including handoff points, verification stages, and common failure modes
Experience setting up design automation flows, scripting for physical design tasks, and improving methodology for timing closure and verification
Demonstrated ability to manage people, projects, and cross-functional collaboration in a technical environment with competing priorities

Desired Qualifications

Experience in front-end design or RTL methodologies is a significant plus and will help you bridge design intent with physical implementation

Benefits

Comprehensive medical and healthcare plans that work for you and your family.
ETO and FTO Programs.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more.
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Save for your future with our retirement plans that vary by region and country.
Competitive salaries.

Skills

ICC2Fusion CompilerPrimeTimeCalibreTempus

#ASIC#Physical Design#Manager#Engineering#Hardware Engineering#Chip Architecture#Circuit Design#Verification#Semiconductor#RTL to GDSII#Timing Closure#Power Optimization#Physical Verification#Design Automation#Foundry Interaction#Testchip

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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