Staff Engineer, Memory Layout Design

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Synopsys is looking for a Staff Engineer to lead memory layout design and automation. This role involves architecting frameworks for generating and verifying custom memory IP layouts at scale, integrating EDA tools, and defining design rules. The ideal candidate will have extensive experience in custom IC layout, automation, and advanced process nodes.

Responsibilities

Lead technology studies and process entitlement evaluations for advanced nodes (FinFET, GAA) to define actionable layout guidelines for embedded memory compiler teams.
Architect and build layout automation frameworks using Python and TCL that generate, verify, and validate custom memory IP layouts at scale.
Develop and maintain automated physical verification flows integrating Synopsys Custom Compiler, StarRC for parasitic extraction, and Ansys Totem for EM/IR reliability analysis.
Author and document physical implementation design rules, best practices, and layout methodologies for SRAM, ROM, and register file compilers.
Evaluate next-generation EDA tools and capabilities, working with vendors and internal teams to define adoption and integration strategies.
Provide technical leadership and mentorship to layout development teams, troubleshooting complex verification failures and flow bottlenecks.
Collaborate with foundry partners on design-technology co-optimization.

Requirements

8+ years of hands-on experience in custom IC layout methodology, EDA automation, or physical design enablement, with a strong focus on embedded memory architectures like SRAM, ROM, or register files.
Deep proficiency in Python and TCL for building production-grade layout automation tools, verification flows, and EDA infrastructure.
Extensive experience developing and deploying automated physical verification flows using Synopsys Custom Compiler, StarRC, Ansys Totem, or equivalent industry-standard tools.
Solid understanding of advanced process nodes (FinFET, GAA, 5nm and below) and the ability to translate complex foundry design rules into engineering guidelines and automation requirements.
Strong working knowledge of DRC/LVS/Antenna checking, EM/IR drop analysis, and parasitic extraction methodologies in the context of full-custom layout.
Bachelor's, Master's, or Ph.D. in Electrical Engineering, Electronics Engineering, Computer Science, or related field with a focus on EDA or layout methodology.

Desired Qualifications

Experience collaborating with foundry teams on design-technology co-optimization or familiarity with AI/ML frameworks for automating engineering tasks is a strong plus.

Benefits

Comprehensive medical and healthcare plans.
ETO and FTO Programs for time away.
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance.
ESPP: Purchase Synopsys common stock at a 15% discount, with a 24 month look-back.
Retirement plans.
Competitive salaries.

Skills

PythonTCLStarRCCustom CompilerAnsys TotemDRCLVSAntennaEM/IR analysisparasitic extraction

#Engineering#Memory Layout#Staff Engineer#Automation#EDA#Python#TCL#Custom Compiler#StarRC#Ansys Totem#Physical Design#FinFET#GAA#SRAM#ROM#Register File

About Synopsys Inc

Smart, Secure Everything—From Silicon to Software Synopsys technology is at the heart of innovations that are changing the way we live and work. The Internet of Things. Autonomous cars. Wearables. Smart medical devices. Secure financial services. Machine learning and computer vision. These breakthroughs are ushering in the era of Smart, Secure Everything―where devices are getting smarter, everything’s connected, and everything must be secure. Powering this new era of technology are advanced silicon chips, which are made even smarter by the remarkable software that drives them. Synopsys is at…

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