Sr. Staff Packaging Engineer- Process Package Integrity & Bumping
Manufacturing & Production · Production & Assembly · Manufacturing Engineering · Process Improvement
In short
As a Sr. Staff Packaging Engineer specializing in process package integrity and bumping, you will lead technology development and new product introduction (NPI) for wafer bumping processes across multiple silicon technology nodes. This role involves defining, optimizing, and qualifying bumping process flows, partnering with suppliers, and ensuring high-volume readiness for advanced packaging solutions.
Responsibilities
- Drive technology development and new product introduction (NPI) for wafer bumping (Far-BEOL) process integration, qualification, and high-volume readiness.
- Define bumping process flows (passivation/UBM/RDL/bump), establish process windows and controls, and lead DOE-based optimization.
- Partner with suppliers to improve yield, reliability, and cost.
- Work closely with foundry FBEOL teams, bumping/assembly partners, and internal teams to deliver robust bumping solutions.
- Lead bumping house/line bring-up, qualification, and ongoing performance management to expand capacity and ensure multi-source readiness.
- Design and drive novel test vehicles/structures for bump/RDL process characterization and process-package interaction.
Requirements
- Expertise in Far-BEOL bumping process modules and integration, including passivation openings, UBM, RDL, solder/Cu pillar bump formation, and associated materials/equipment.
- Deep knowledge of flip-chip bump design intent and assembly interactions, and wafer-level packaging (RDL) / fan-out process considerations impacting bumping.
- Strong technical skills in bumping process/material/equipment characterization, failure analysis, DOE design, statistical data analysis, and FMEA.
- Experience leading bumping process qualification and production release activities for NPI and high-volume manufacturing.
- Proven track record enabling package development through robust bumping solutions for flip-chip, RDL/fan-out RDL, and advanced packaging technologies.
- Expertise in manufacturing execution for Far-BEOL bump structures and bump line operations, including new bumping line bring-up, tooling/equipment qualification, and production ramp.
- Hands-on experience in project leadership and supplier management for external bumping houses/OSATs.
- Experienced interfacing with foundries and bumping houses on process integration, change control, line qualification, and multi-source/capacity expansion.
- Understanding of heterogeneous integration (2.5D/3DIC) packaging flows and how bumping/interconnect schemes impact downstream assembly and reliability.
- Experience with chip and substrate design tools such as Calibre, Virtuoso, CAD, SiP, and GDS.
- Understanding of chip-top physical design flow and communication with package design teams.
- Minimum of 8–10 years hands-on experience in silicon interconnect process, bumping and/or RDL process, new technology qualification and production.
Desired Qualifications
- Bachelor's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 6+ years of System/Package Design/Technology Engineering or related work experience.
- Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 5+ years of System/Package Design/Technology Engineering or related work experience.
- PhD in Chemical Engineering, Electrical Engineering, Mechanical Engineering, or related field and 4+ year of System/Package Design/Technology Engineering or related work experience.
- Good analytical and project management skills.
- Excellent capability of innovation and creativity.
- Highly motivated and committed to success of the individual and the team.
- Superior interpersonal communication skills. Publish technical reports.
- Able to work flexible hours.
Benefits
- Competitive annual discretionary bonus program.
- Opportunity for annual RSU grants.
- Highly competitive benefits package designed to support your success at work, at home, and at play.
- Occasional domestic/international travels needed.
Skills
passivationUBMRDLsolderCu pillarflip-chipDOEFMEASPCCalibreVirtuosoCADSiPGDS
#Packaging Engineering#Process Package Integration#Bumping Process#Far-BEOL#Wafer Bumping#NPI#OSAT
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
3 weeks ago
Employment Type
Full Time
Work mode
On Site
Salary
US$191,800–287,800 / year
Experience Level
Senior
Locations
San Diego, United States of America
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
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