SOC Debug Engineer

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is looking for an experienced SOC Debug Engineer to define and deliver next-generation system-on-chip (SoC) products, focusing on RISC-V architecture, debug, and security. The role involves creating scalable SoC architectures, collaborating with cross-functional teams, and performing trade-off analysis to optimize solutions.

Responsibilities

Create highly scalable SoC architecture with expertise in SoC control, boot, reset, timebase management, debug, and micro-controllers.
Comprehend product requirements to steer generation of proper architecture.
Perform trade-off analysis in the solution space to produce the most optimal architecture.
Collaborate with architects, technical leads, hardware and software engineers from various functional areas in deriving the architectural solution.
Generate detailed architectural specifications and work closely with the design team to implement the architecture.

Requirements

Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Experienced in ARM and RISC-V AP architecture.
Excellent communication, documentation, and interpersonal skills with ability to convey proposals and interact effectively across a distributed multi-discipline organization.
Strong foundation of silicon design principles and architectural trade-offs.
Ability to span and connect levels of abstraction across system-design, high-level languages, OS, HW/SW interface, micro-architecture, and silicon implementation.
Background in architecture (IP or SoC), and/or front-end design/verification (micro-architecture).
Demonstrated deep technical knowledge and achievements at the SoC, sub-system or large IP levels as micro-architect or architect.
Ability to apply appropriate abstractions and quantitative analysis for problem definition and solutions.
Experience in using, improving, and developing a variety of tools for analysis and modeling, such as functional and performance simulators, profilers, etc.
Programming ability for modeling and automation (OOP C++, Python preferred) with experience in software development best practices including reviews, unit-testing, version control, etc.
Ability and desire to develop and improve architecture methodologies for experiments and analysis.
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.
OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience.
OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Desired Qualifications

Preferred with experience in the SoC areas such as boot, timebase management and network, security architecture, reset architecture and debug architecture, system level control/management with components such as BMC, ECU, etc.
Bachelor’s degree in Electronic Engineering, Computer Science or related field required; Master’s degree or PhD highly desired
5+ years of SoC/IP architecture or micro-architecture/front-end-design
Candidates with primarily a micro-architecture/design background must have contributions that demonstrate higher-level analysis and design
SoC architectures including heterogeneous compute, NoC/interconnect, memory-systems, multicore, multi-die, cache hierarchies, shared memory, I/O, coherency, compression, security
Resource and Power Management
Security Architecture
System-level debug
Safety, reliability, and high-resilience/high-availability systems
AI & Machine Learning
Control and Real-time systems
High-level Operating Systems (e.g., Android, Linux, Windows)
Real-time operating systems (e.g., Zephyr, FreeRTOS)
Front-end Digital Hardware Design or Verification
Arm system architectures (e.g., Cortex-A, Cortex-R, Cortex-M, CoreSight)
High-speed I/O (USB, PCIe, CXL)
External memory and storage architectures (e.g., LPDDR, NAND Flash, NOR Flash)
Networking & Connectivity (e.g., Ethernet, WLAN, Cellular, CAN)
Behavioral, functional and performance modeling
Power and/or performance optimization through simulation & modeling
Simulator architectures and frameworks (C++ or Python-based preferred)
Analytical modeling for performance and power

Benefits

Competitive annual discretionary bonus program
Opportunity for annual RSU grants
Highly competitive benefits package designed to support your success at work, at home, and at play.

Skills

PythonC++ARMRISC-VLinuxAndroidWindowsZephyrFreeRTOSPCIeUSBEthernetWLANCAN

#SoC#Debug#Engineer#ASIC#RISC-V#Architecture#Verification#Validation#Integration

About Qualcomm

Enabling a world where everyone and everything can be intelligently connected.

Enabling a world where everyone and everything can be intelligently connected.\n\n

See all open jobs at Qualcomm Read more about Qualcomm Website

Company

Qualcomm

Job Posted

2 weeks ago

Employment Type

Full Time

Work mode

On Site

Salary

US$145,600–218,400 / year

Experience Level

Senior

Locations

San Diego, United States of America

Qualification

Bachelor, Master, Doctoral

Applicants

Be an early applicant

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