NPU Design implementation (Synthesis) Principal/Manager

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

The NPU Synthesis Lead will drive synthesis and timing closure for Neural Processing Unit (NPU) IP and subsystems in cutting-edge SoCs, optimizing for PPA and collaborating with cross-functional teams. This role requires deep expertise in ASIC design flow, synthesis tools, low-power design techniques, and leadership skills for team mentoring and best practice dissemination.

Responsibilities

Lead RTL-to-gate-level synthesis for NPU IP and subsystems using industry-standard tools (Synopsys Design Compiler, Cadence Genus).
Develop and maintain synthesis scripts and flows for hierarchical and flat designs.
Drive pre-layout and post-layout timing closure across multiple voltage and process corners.
Collaborate with STA teams to resolve setup/hold violations.
Apply physical-aware synthesis techniques to meet aggressive PPA targets.
Implement low-power strategies using UPF/CPF flows.
Validate and maintain SDC constraints for clocks, I/O delays, multi-cycle paths, and false paths.
Work closely with RTL design, DFT, and physical design teams for seamless handoff.
Provide feedback to architecture and RTL teams for QoR improvements.
Perform LEC (Logical Equivalence Check), CLP (Clock/Power checks), and linting.
Explore advanced synthesis methodologies and EDA tool capabilities for better QoR.
Mentor junior engineers and drive best practices across synthesis and timing teams.

Requirements

Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Strong knowledge of ASIC design flow: RTL → Synthesis → STA → P&R.
Proficiency in synthesis tools (Design Compiler, Genus) and STA tools (PrimeTime).
Experience with UPF/CPF-based flows and multi-voltage designs.
Advanced skills in Tcl, Perl, Python for automation.
Familiarity with Spyglass, Lint, CDC tools, and power analysis tools.
Ability to lead synthesis teams and coordinate with cross-functional groups.
Bachelor’s/Master’s in Electrical Engineering, Computer Engineering, or related field.
15+ years in ASIC synthesis and timing closure, with at least 3 years in NPU or AI processor design.

Desired Qualifications

Experience with advanced nodes (5nm/3nm), hierarchical synthesis, and physical-aware flows.
Prior tape-out experience for NPU or DSP cores.

Benefits

Qualcomm is an equal opportunity employer.
Qualcomm is committed to providing an accessible process.
Qualcomm is committed to making our workplace accessible for individuals with disabilities.

Skills

Design CompilerGenusPrimeTimeTclPerlPythonSpyglassLintCDCUPFCPF

#NPU#Synthesis#Timing Closure#PPA Optimization#ASIC Design#Hardware Engineering#Low Power Design#EDA Tools

About Qualcomm

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Enabling a world where everyone and everything can be intelligently connected.\n\n

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Company

Qualcomm

Job Posted

2 weeks ago

Employment Type

Full Time

Work mode

On Site

Experience Level

Executive

Locations

Bangalore, India

Qualification

Bachelor, Master, Doctoral

Applicants

Be an early applicant

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NPU Design implementation (Synthesis) Principal/Manager

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