NPU AI/Processor Synthesis Engineer- Sr Staff
Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems
In short
We are seeking a Sr Staff Synthesis Engineer to join our NPU design team in Bangalore, India. This role involves driving RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators, collaborating with multiple engineering teams to achieve PPA targets on advanced technology nodes.
Responsibilities
- Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
- Develop and maintain synthesis flows, constraints, and automation.
- Drive pre-layout and post-layout timing closure across multiple modes and process corners.
- Optimize designs for PPA (Performance, Power, Area) targets.
- Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.
- Collaborate with RTL, DFT, STA, and Physical Design teams.
- Perform quality checks including LEC, CDC, lint, and low-power verification.
- Analyze and improve synthesis QoR through scripting and flow enhancements.
- Support tapeout activities and drive continuous improvements in synthesis methodologies.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
- Strong understanding of ASIC design flow from RTL to GDS.
- Hands-on experience with RTL synthesis, timing closure, and constraint development.
- Expertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
- Strong timing analysis knowledge using PrimeTime.
- Experience with low-power design methodologies and UPF-based flows.
- Good understanding of clocking architecture, timing constraints, and timing signoff.
- Proficiency in TCL and scripting languages such as Python or Perl.
- Excellent debugging, problem-solving, and cross-functional collaboration skills.
Desired Qualifications
- Experience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.
- Knowledge of advanced technology nodes (5nm, 4nm, 3nm and below).
- Experience with physical-aware synthesis and hierarchical design methodologies.
- Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
- Proven track record of successful SoC or IP tapeouts.
Benefits
- Qualcomm is an equal opportunity employer.
- Commitment to providing an accessible process for individuals with disabilities.
- Possibility of reasonable accommodations for individuals with disabilities.
- Commitment to making the workplace accessible for individuals with disabilities.
Skills
TCLPythonPerlSynopsys Design CompilerFusion CompilerCadence GenusPrimeTimeUPF
#AI#NPU#Processor#Synthesis#ASIC#Engineering#RTL#GDS#Timing Closure#Accelerators#SoC#Technology Nodes
About Qualcomm
Enabling a world where everyone and everything can be intelligently connected.
Enabling a world where everyone and everything can be intelligently connected.\n\n
Company
QualcommJob Posted
3 days ago
Employment Type
Full Time
Work mode
On Site
Experience Level
Senior
Locations
Bangalore, India
Qualification
Bachelor, Master, Doctoral
Applicants
Be an early applicant
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