NPU AI/Processor Synthesis Engineer- Sr Staff

Technology, Data & Digital · Software & Web Development · Software Engineering · Embedded Systems

In short

Qualcomm is seeking a Sr Staff Synthesis Engineer for their NPU AI/Processor design team in Bangalore, India. This role is responsible for driving RTL-to-GDS synthesis and timing closure for high-performance AI/ML accelerators. The engineer will collaborate with cross-functional teams and optimize designs for PPA targets on advanced technology nodes.

Responsibilities

Own RTL-to-gate synthesis and timing closure for NPU IPs and subsystems.
Develop and maintain synthesis flows, constraints, and automation for complex hierarchical designs.
Drive pre-layout and post-layout timing closure across multiple modes and process corners.
Optimize designs for PPA (Performance, Power, Area) targets using physical-aware synthesis methodologies.
Create, validate, and maintain timing constraints (SDC), clock definitions, false paths, and multi-cycle paths.
Collaborate with RTL, DFT, STA, and Physical Design teams to resolve QoR, timing, power, and convergence issues.
Perform quality checks including LEC, CDC, lint, and low-power verification.
Analyze and improve synthesis QoR through scripting and flow enhancements.
Support tapeout activities and drive continuous improvements in synthesis methodologies.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or related field.
Strong understanding of ASIC design flow from RTL to GDS.
Hands-on experience with RTL synthesis, timing closure, and constraint development.
Expertise in Synopsys Design Compiler/Fusion Compiler or Cadence Genus.
Strong timing analysis knowledge using PrimeTime.
Experience with low-power design methodologies and UPF-based flows.
Good understanding of clocking architecture, timing constraints, and timing signoff.
Proficiency in TCL and scripting languages such as Python or Perl.
Excellent debugging, problem-solving, and cross-functional collaboration skills.

Desired Qualifications

Experience working on AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.
Knowledge of advanced technology nodes (5nm, 4nm, 3nm and below).
Experience with physical-aware synthesis and hierarchical design methodologies.
Familiarity with LEC, CDC, lint, power analysis, and low-power verification flows.
Proven track record of successful SoC or IP tapeouts.