Master Thesis: Requirements-Driven Verification of DFE Hardware using AI Tools

Technology, Data & Digital · Software & Web Development · Embedded Systems · Software Engineering

In short

This Master Thesis project in Stockholm, Sweden, focuses on developing and evaluating a methodology for using AI tools to create verification material for Digital Front-End (DFE) hardware. You will work with system requirements and design specifications to generate verification plans, test scenarios, assertions, and testbenches, assessing the AI-generated outputs for correctness and completeness.

Responsibilities

Derive verification objectives, test scenarios, checking methods, coverage goals, and traceability to requirements using a methodology.
Use AI tools to identify corner cases and develop directed and constrained random test stimuli.
Generate System Verilog Assertions for interfaces, control logic, data processing, timing, and error handling, followed by technical review.
Create or prototype a suitable testbench structure with drivers, monitors, checkers, scoreboards, and test control.
Investigate whether a functional reference model can be generated or adapted for comparison with the RTL implementation.
Assess the AI-generated verification material for correctness, completeness, traceability, and usefulness in simulation.
Describe the methodology, results, limitations, and recommendations for future work in a thesis document.

Requirements

Master´s student in electrical/computer engineering, embedded systems, or similar.
Digital design and computer architecture fundamentals.
Experience with System Verilog and RTL simulation tools.
Basic knowledge of digital signal processing or communication systems.
Understanding verification concepts such as assertions, coverage, scoreboards, and reference models.
Programming experience in Python, C/C++, or a similar language.
Ability to understand requirements and design specifications.
Good analytical, communication, and documentation skills in English.

Desired Qualifications

Experience with UVM, formal verification, testbench development, scripting, AI data processing pipelines, prompt design, or hands-on experience with AI-tools.

Benefits

Outstanding opportunity to use your skills and imagination to push the boundaries of what's possible.
Challenge and grow within a team of diverse innovators.
Opportunity to craft what comes next.
Be part of a company that champions diversity and inclusion.

Skills

System VerilogRTL simulationPythonC++UVMformal verificationprompt design

#Master Thesis#DFE Hardware#AI Tools#Verification#Requirements Engineering#System Verilog#RTL Simulation#Python#Digital Signal Processing#Computer Engineering

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